Device Packaging 2019

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Reliability of Fan-Out Wafer-Level System-in-Package
Keywords: FOWLP, Reliability, SiP
In this study, the reliability (thermal-cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) with one larger chip of 5mmx5mm and three smaller chips of 3mmx3mm embedded in an epoxy molding compound (EMC) package (10mmx10mm) with two RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level SiP is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a 6-layer PCB. The sample sizes for the thermal-cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal-cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out package during thermal-cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.
John H Lau,
ASM Pacific Technology
Hong Kong, Hong Kong
China


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