Device Packaging 2019

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Enabling High-Performance Heterogeneous Integration via Interface Standards, IP Reuse, and Modular Design
Keywords: heterogeneous integration, IP reuse, interface standards
Heterogeneous Integration at DARPA The DARPA Microsystems Technology Office (MTO) has driven the development of revolutionary materials, devices, and integration techniques to meet the performance requirements for the most advanced electronic systems [1,2]. In particular, the Compound Semiconductor Materials on Silicon (COSMOS) program focused on the development of new methods to tightly integrate compound semiconductor (CS) technologies within state-of-the-art silicon CMOS circuits in order to achieve unprecedented circuit performance levels [3-8]. More recently, the Diverse Accessible Heterogeneous Integration (DAHI) program continued that work by developing heterogeneous integration processes to intimately combine advanced CS devices and other device technologies with high-density silicon CMOS technology in a foundry setting [9-13]. CHIPS Program Overview Now, DARPA has a new thrust to leverage mainstream semiconductor design approaches to enable the rapid and cost-effective integration of heterogeneous device technologies. This represents a leap ahead beyond the monolithic silicon approach that has served the semiconductor industry well, but which now creates prohibitive cost and design issues at leading-edge nodes, as well as performance constraints without the benefits of broad device technology options. Specifically, DARPA�s Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program will develop interface standards, IP reuse methodologies, and modular design approaches with the goal of making heterogeneous integration as straightforward as printed circuit board design and assembly, without compromising device performance [14]. To enable the vision of seamless integration of diverse device technologies, interface standards are needed to foster a CHIPS eco-system. The CHIPS methodology will be adopted only if designers throughout the industry can design chiplets to a known interface standard. (Additionally, the existence of a CHIPS standard will be a self-reinforcing scenario � the use of the standard by chip designers will broaden its utility, thus encouraging more designers to make use of it.) While there are numerous parallel and serial interface standards in the industry, they are typically for specific functions, such as the High Bandwidth Memory (HBM) DRAM standard codified in JEDEC�s JESD235A standard. The CHIPS program is driving convergence on an interface standard that will likely leverage existing standards but is also tailored for the specific technical requirements of connecting chiplets in applications that can benefit the most from modularization. The second pillar of the CHIPS approach is IP resuse. To save time and money � measured in years and millions of dollars � it is typical in monolithic chip design to reuse verified IP blocks for common functions. For heterogeneous systems, though, this IP infrastructure is lacking because of the n-fold (or worse) increase in the challenge when multiple technologies are integrated. With a standard CHIPS interface for heterogeneous integration, IP reuse is enabled at the chiplet level. Heterogeneous design will become essentially the same as monolithic design, with the knowledge that IP blocks can be integrated successfully. Finally, a modular design paradigm is needed to enable designers to take full advantage of interface standards and heterogeneous IP reuse. Design tools and process design kits (PDKs) will account for different device technologies and their integration, with the appropriate design, simulation, and analysis capabilities in place. CHIPS Program Structure and Status The CHIPS program is structured in two Technical Areas (TAs) � Modular Digital Systems (TA1) and Supporting Technologies (TA3). TA1 performers are Boeing, Intel, Lockheed Martin, Northrop Grumman, and the University of Michigan. Each of the TA1 performers is designing a system using the CHIPS approach, and the teams are also collaborating to specify and implement an interface standard. Since convergence on the interface standard is required before designs can be finalized, this is the first major milestone in the CHIPS program. The definition of the CHIPS interface standard is expected in Q2 2018. The TA3 performers will provide IP blocks and design tools that will be used by TA1 designers, although the IP blocks and design tools will be developed with broader usage in mind. Performers developing design tools are Georgia Tech and Cadence, while IP blocks are being developed by Intrinsix, Jariet Technologies, Micron Technology, North Carolina State University, and Synopsys. The system designers of TA1 will also be providing IP blocks. To ensure successful integration, the CHIPS program is also pursuing multiple integration strategies. The first will be a leading edge but broadly available industry standard interconnect on a silicon interposer, while at least one other approach with much finer pitch will be developed in parallel for Phase 2 of the four-year program. Early results on integration technology are expected in 2018.
Jeffrey C. Demmin, Sr. Lead Scientist
Booz Allen Hamilton
Arlington, VA

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