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Wire Bonding Advances for Multi-Chip and System in Package Devices
Keywords: Wire Bonding, SSB, Multi-chip packaging
Along side the rapid growth of advanced electronic packaging technologies such as 3D packaging and wafer level packaging, wire bonding continues to be the most dominant interconnection technology used in the electronic packaging industry. Wire bonding remains popular due to its low cost, high yield rate, increased flexibility and improved reliability. A type of wire bonding, Stand-Off-Stitch Bond (SSB), is widely used in many Multi-chip and System in Package (SiP) applications, including light-emitting diodes (LEDs) and stacked-die memory devices, to provide die-to-die interconnections. The SSB process starts with a flat-topped bump bonding on the substrate or die, followed by the formation of a new ball bond (1st bond) on the die or substrate. The stitch bond (2nd bond) of that wire is bonded on top of the initial bump. If the bump is on die pad, it is referred to as reverse-bonded SSB, and is commonly used for ultra-low loop applications. This paper will review a variety of SSB applications, as well as the pros and cons of different bump shaping methods. It also discusses the pros and cons of commonly used bonding wire types, including Au wire, Ag alloy wire, bare Cu wire, and Pd coated Cu wire. In general, higher elongation wires (e.g. Au wire and bare Cu wire) are difficult for bump shaping, e.g. they have a small or non-existent short tail to long tail window. The bonding tool (e.g. capillary) also has a significant effect on the bump shaping process, which will also be discussed. This paper further examines the main challenges and solutions of SSB applications. For LED Au wire applications, bump shaping is very challenging as Au wire has large elongation property. As for fine pitch die-to-die SSB applications using Cu wire, bump lift during bump shaping, bump long tail and 2nd bond non stitch on bump are the main issues. We study various bump shaping parameters including Bump Mode, Smooth Method, Separation Height and Bump Height, as well as bump bonding, stitch (on bump) bonding and looping parameters. We demonstrate both Au wire and Cu wire SSB capability using newly developed processes, including 18 µm (0.7mil) 99.99 wt% Au wire processes for fine pitch RGB LED applications, and ultra-fine pitch 15 µm (0.6mil) Cu wire processes for sub-20 nm node wafer technology.
Hui Xu, Staff Engineer, Team Lead
Kulicke and Soffa Industries, Inc.
Fort Washington, PA

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