Device Packaging 2019

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Status on 3D Stacking Using Direct Hybrid Bonding
Keywords: hybrid bonding, 3d stacking, heterogeneous integration
In the context of High Performance Computing, Networking, and Big-Data applications, the never-ending quest of computing requires very large systems, fully scalable, easy to program, with reduced cost and high energy efficiency. Proximity of huge quantity of memory is one of the key challenges to address, while keeping in mind the 'energy-cost' of large data transfers. Until now, designers used to develop their components in advanced nodes technology to meet those requirements. Nevertheless, considering all challenges, in addition to the fact that cost design is dramatically unaffordable for most of the players, going to heterogeneous integration and modular stacking is gaining more and more interest. Some of the key advantages of heterogeneous integration compared to classical planar architecture are the following: - The number of transistors, or functions by surface unit increase - Possible re-use of advanced IPs, which allows faster time-to-market as well as cost decrease - Use the right technology node for the right function. To do so, the first challenge of heterogeneous integration in this context is to maintain or even decrease the energy efficiency of the global system. Several solutions are already available in foundry or OSAT to go in that direction, mainly driven by TSMC with InFo advanced packaging, or Intel with EMIB. Nevertheless, the current solutions may meet some hard stop challenges concerning the overall consumption: high density of interconnect between separate functions (mainly logic to memory) is absolutely required, with an objective of less than 1pJ/bit per vertical link. This figure of merit leads naturally to very high density of 3D interconnects, less than 10µm and even less than 5µm. Direct hybrid bonding using Cu / Si02 interconnects have gained huge interest during the past 5 years, mainly driven by 3D-stacked Back-side Imagers, with some achievements in the range of few micrometers of pitch using Wafer-to-Wafer bonding technology. In this paper, CEA-Leti will describe the key process steps to achieve 1µm of pitch for a Wafer-to-Wafer integration. Additionally, we are convinced that Die-to-Wafer is of high interest for advanced nodes die stacking or for interposer. This paper will also describes the flow to achieve a die-to-wafer integration, the challenges in regards to a Wafer-to-Wafer integration. In particular, the recent work achieved with the equipment supplier SET, will be described. Finally, aware that throughput of Die-to-Wafer approach could be a showstopper to the die-to-wafer direct hybrid bonding technology, CEA-LETI worked since 2010 on an alternative self-assembly process that could enable, once optimized, to at least double the throughput. Self-Assembly process is based on the use of a water droplet to align top on bottom die thanks to capillary tension which will be the driving force for die alignment (corresponding to the minimal liquid/air surface). The concept of this innovative promising technology will be reminded, and recent results will be given. At the end, CEA-Leti will provide with some mid to long term perspectives in terms of potential applications. This work was funded thanks to the French national program 'Programme d'Investissements d'Avenir, IRT Nanoelec' ANR-10-AIRT-05.
Bruno Paing,
Grenoble, Fr

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