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|Comparison of Advanced Thermal Solutions for Laminate Designs|
|Keywords: thermal, FEA, vias|
|To accommodate growth in demand for high-powered modules in the semiconductor industry, applying Fourier’s Law of heat transfer to the laminate substrate thermal path can help us optimize module design thermal performance. Vias in laminate substrates are standard as both an electrical and thermal path for the die to the ground pad of the package. A common way to increase the thermal performance of a higher powered module is by increasing the via density on the ground pad of a laminate substrate. A step further to increasing via surface area is by using slot vias. Slot vias are drilled with the same diameter as a standard via but can extend to any length along the laminate. Altering the shape of the via, such as a star shape, can be used to increase the surface area. Thermal slugs are coins made of various thermal conductive materials that insert into a predrilled cavity in the laminate and held in with an epoxy fill material. In most cases, thermal slugs will provide the maximum surface area to transfer heat in a laminate substrate. To shorten this thermal path even further, we can also mount the die directly in this cavity on a plated surface with a thin layer of epoxy. When evaluating package and PCB substrate thermal design options it is good to quantify performance differences to determine if the system will be able to sufficiently cool down components. Hand calculations may work for simple configurations, but for complex systems it is best practice to complete thermal simulations using a commercial CFD or FEA software package such as ANSYS Icepak, ANSYS Mechanical, or Mentor Graphics FloTHERM. For this evaluation, we used ANSYS Icepak to complete thermal simulations of a 5x5 mm LGA device. First, we simulated a package with hollow plated vias, solid vias, slot vias, heat slug, and die-in-cavity configurations to characterize the thermal resistance from die surface to package bottom, which varied between approximately 0.8°C/W to 2.3°C/W when using the different thermal structures. Second, we simulated the best and worst performing package configurations on a thin PCB with drilled and plated hollow vias. We then evaluated second level solder voiding with these configurations by adding a single, centered solder void covering between 10-50% of the total ground paddle area. Die junction to PCB bottom thermal resistance ranged between approximately 2.7°C/W to 8.0°C/W across different package and voiding combinations.|
|Eric Eilenberg, Packaging Engineer
Newport Beach, CA