Here is the abstract you requested from the Thermal_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|A Thermal Model Profiling Temperature of High Power Density ASIC Device Mounted on Multi-layered Diamond Enhanced Heat Spreader|
|Keywords: Heat spreader, CVD Diamond, Model|
|When comparing synthetic diamond against its ceramic counterparts, the former delivers benefits for a diverse range of industries and applications. This especially applies to thermal applications, where diamond thermal conductivity is far superior to other materials available on the market. Significant improvements to electronic systems can be realized by using CVD diamond heat spreaders. Integration is relatively straightforward, as CVD diamond can be a direct replacement for aluminum nitride (AlN), BeO, or other advanced ceramics. However in this presentation in a new approach, CVD diamond is combined with other heat spreaders and the results are modeled and presented. Using Comsol the effects of stack geometry, surface flatness, material thermal conductivity and solder uniformity is evaluated. Impact of changing diamond and other material thermal conductivity on an ASIC device heating is demonstrated and practical issues such as heat spreader flatness and uniformity of thermal interface thickness on device temperature is examined. Effect of hot spot size from 0.1 mm x 1.5 mm to 0.4 mm x 2.0 mm and channel numbers for 1 to 10 hot channels per die operating at 10 to 50 Watts (50% duty cycle) is evaluated. The model consists of a section where geometry and material properties of each component of the design are defined. This includes a silicon ASIC, a diamond heat spreader with a corresponding solder layer, a second diamond or other heat spreader and a corresponding solder layer and a final heat spreader layer with a final solder layer. Two additional sections for development of the mesh and the simulation section are created and visualised. The simulation section includes two simulation options with corresponding graphs. In the steady state simulation section, the power per channel of the ASIC is an input parameter entered by the user. The result of the simulation is presented in both 2D and 3D. For 3D, the computed temperature field in the whole geometry is shown, and in the 2D cross-section an XZ plane crossing the middle of the hot channels and an ASIC surface temperature that is crossing the middle of the hot channels showing the thermal crosstalk between the hot channels is simulated and presented. In the transient simulation section, the simulation accepts the peak power per channel and the frequency and duty cycle of the heating profile as input. By default only one period is simulated, but it is possible to use the model and simulate for additional periods. Simulation time is proportional to the number of simulated periods.|
|Firooz Faili, Head of CVD Thermal Products
Element Six Technologies, USA
Santa Clara, CA