Honeywell

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Software framework for rapid design of multi-chip modules
Keywords: Multi-Die Packaging, Additive Manufacturing, Software Tools
Multi-chip modules are complex systems that require a broad range of expertise to design and fabricate successfully. One roadblock often encountered is that design tools are segmented by discipline, optimized for legacy production methods and lacking the flexibility required to rapidly consider design changes ranging from component selection to alternative fabrication processes. To overcome these issues, we have developed a framework of software tools that enables multi-chip modules to be designed, redesigned and evaluated quickly and flexibly, without the constraints often imposed by corporate software packages. In this work, we will demonstrate how this tool allows us to redesign, reformat and layout a simple sample circuit in a variety of ways spanning various fabrication techniques. Automated analysis spanning structural, thermal and electrical domains demonstrate the flexibility of the tools for optimization of a design across disciplines. For convenience, the sample circuit we chose for this work was based off an Arduino mini design, featuring more than thirty low cost consumer off the shelf components including a Bluetooth module and current measurement sensor. Traditionally, the device schematic is laid out using a printed circuit board computer aided design software package like a product from Autodesk or Mentor Graphics, after which parts are placed on the top layer, and routed before being sent out for fabrication and assembly. To reduce the overall footprint of the device, we chose to place as many components as we could atop other components. By utilizing up to three layers of stacked components, we were able to place the components using commercial software in this configuration and reduce the overall footprint by more than half while reducing the overall volume slightly, but were unable to route traces in such a way as to make the device’s fabrication possible using conventional PCB methods. Since other fabrication methods are not supported by these software tools, we developed a more flexible tool that enabled us to route the component stack up for fabrication using additive manufacturing, and link up to finite element solvers to seamlessly answer questions related to signal integrity or thermal stress resulting from the alternative layout. While this device was incredibly simple, the framework is one which is extensible to systems of smaller size scales that include die or wafer stacks. Some limitations on the tool are related to the NP completeness of well-studied computational problems and the availability of computational resources. At present, the tool would benefit from an overhaul of its underlying data structures which are not optimized for minimized memory usage.
Isaac Ehrenberg,
Draper
Cambridge, Massachusetts
United States


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