Here is the abstract you requested from the dpc_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|The bifurcation of advanced IC packaging|
|Keywords: Advanced packaging, Heterogenous integration, Design flows|
|The bifurcation of advanced IC packaging John Park -Product Management Director Cadence Design Systems Abstract Following a similar trend from the 1990’s, IC package design is experiencing a sea change. As a refresher, the 1990’s is when the ball grid array (BGA) came along, introducing a whole new set of design tool requirements. The mechanical design tools used for the previous generation of lead frame styled packages were no longer capable of supporting the new design requirements of the BGA. In short, the BGA introduced multi-layer routable organic and ceramic substrates and new possibilities for stacking (and embedding) multi-die, requiring designers to abandon their mechanical design tools and look at new solutions for doing package design. On top of that, IO’s were switching faster than ever, requiring engineers to look at new ways of electrically characterizing these designs. As a result, a couple of EDA companies stepped up and adapted their printed circuit board (PCB) layout and analysis tools for that generation of BGA-based advanced packaging. Problem (more or less) solved! Fast forward to today and we see a very similar trend. Now being introduced at a rapid pace, are new advanced IC packaging solutions that have a lot more silicon content, wafer stacking and, in some cases, chips being packaged directly at the wafer- level at traditional IC foundries, skipping the traditional OSAT model of the past. Make no mistake, this is a significant change to the status quo of BGA package design tools of the past. The PCB-like flows that were established for BGA design are likely not the path forward for technologies like, 2.5D/3D IC and fan-out wafer-level packaging (FOWLP). Instead, in all likelihood IC design tools and flows will need to be slightly adapted to support the next generation of package designs. Let’s start with foundry-based FOWLP. In this case, induvial dice are placed on a chip-carrier with additional spacing between them. Molding is poured in the empty space and then an array of bumps (UBM) and the connectivity (RDL) are added. In foundry-based flows, these UBM and RDL layers require IC-styled routing/metal fill and mask generation from the layout tool. In addition, these masks must be verified with traditional IC DRC/LVS tools. It’s clear that some kind of hybrid advanced packaging flow using some traditional IC tools in the flow is required to support this type of design. And in fact, if you look at the largest semiconductor foundries reference flow tools, you will find this to be true. This presentation further examines the design tool/flow requirement for FOWLP, 2.5D/3D IC and future multi-die packaging technologies.|
|The bifurcation of advanced IC packaging, Product Managment Director
Cadence Design Systems
San Jose, CA