Here is the abstract you requested from the dpc_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Design, Processes & Technology Co-design Methodology for Advanced Package Assembly in HVM|
|Keywords: Assembly and material optimization , simulation analysis, die & package co-design optimization|
|Costs, design complexity and manufacturing risks are creating opportunities with a rapid convergence of the traditional IC design and IC package design processes. For the goal of achieving the electrical (SI/PI) performance requirements of a complex SoC design, choices of package technology, impact of material selection, process flow optimization are critical factors with increasing challenges to overcome. We have undertaken a co-design methodology to optimize the IC chip layout and substrate design to streamline assembly processes while assimilating the physical and logical interactions within each design domain. We have optimized the die top-level/RDL layout & pattern, defined bump placement & structures for the current density, established electrical constraints for critical nets, applied PG supply strategy, and facilitated routings in the package thereby mitigating assembly risks. To streamline the design and development process, we have employed simulation tools for a thorough evaluation of electrical, mechanical and thermal performance to identify the areas of enhancing the packaging assembly processes: 1) Cadence XtractIM and Ansys SIwave to assess current density and electrical performance on the combo of die + package. 2) Ansys mechanical to understand the underlying assembly issues such as stress induced to die and bumps. 3) Mentor Graphics Flotherm to evaluate the thermal performance per the different die thickness and bump stackup. Using simulation results as the guideline, we have defined and conducted DOEs focusing on bump structures and stackup, die thickness, substrate stackup, assembly mold processes (CUF vs MUF), die placement and configuration, and low CTE material selection to mitigate underlying assembly issues and refine the assembly recipes. We have gained a thorough understanding of dependency factors on the assembly manufacturing processes and parameters in each DOE to finetune and finalize the assembly PORs for the advanced package technology. The refined assembly recipes have delivered the robust package performance and reliability for high volume production.|
|Diane Peng, PMTS, Packaging Engineering