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High Density Thin Organic Substrate for Advanced Flip Chip Package
Keywords: thin substrate, advanced flip chip, 2.1D
Advanced semiconductor packaging requirements for higher and faster performance in a thinner and smaller form factor continue to grow for mobile, network and consumer devices. While the increase in device input/output (I/O) density is driven by the famous Moores Law, the packaging industry is experiencing opposing trends for more complex packaging solutions while the expected cost targets are moving in a downward direction. Fine line/space is one of the key requirements for high I/O count packages where die to die or die to memory integration is needed. Typically, Si based inorganic interposers have been used in this area for the last few years. However, Si interposers are expensive and supply chain issues can be a serious bottleneck. Demand for high speed flip chip packages create an opportunity for highly integrated, multi-chip modules (MCMs) and 2.5D/3D silicon (Si) interposer packages which are emerging very slowly now due to the higher costs often associated with infrastructure and supply chain challenges that can happen before a technology is mature. Achieving both increased margins in the power delivery and increased functionality in next generation high speed applications requires extremely efficient, low loss package designs with an ultra thin core or coreless substrate with fine line and space. As the substrate gets thinner, it becomes very flexible and one of the biggest assembly challenges for ultra thin coreless substrates is to keep the substrate flat during the assembly process while still maintaining yield targets. Other issues with thin substrates are related to post assembly such as handling, long term package reliability and functionality in the application field. The work presented in this paper describes key factors for mitigating several assembly related issues in the manufacturing line, including package warpage/coplanarity, and selecting the optimum processes and materials for ultra thin coreless substrate flip chip packages with high assembly yields. Potential application spaces including die to die and package to package, such as 2.5D or 2.1D methods, will be explored using an ultra-thin coreless substrate as an interposer, as opposed to traditional Si interposer. Various pros and cons along with relative cost data will be discussed. A design of experiment (DOE) for ultra thin substrates is being carried out to achieve the objective of the work. A test vehicle has been designed using a flip chip package with an ultra thin coreless buildup substrate utilizing various assembly materials and processes. The detailed process and some reliability data will be published. More work will be carried out to expand the scope of the technology for multi chip module (MCM) die and 2.5D integration. Some initial 2.1D data will be published as well.
Nokibul Islam,
JCET
Fremont, CA
USA


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