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Development of High Density RDL Technologies for Panel Level Processing
Keywords: Embedded die, Panel level packaging, High density RDL
Advanced packaging technologies like wafer-level fan-out and 3D System-in- Packages (SIPs) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix. At first dies with Cu pillar structures are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15 μm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305x256mm panel format, aiming for a final size of 610x615 mm. On the top side of embedded chips, a 20μm dielectric film is applied. The goal is to avoid additional via formation and to realize a direct connection between the Cu pillar of the die and the RDL The RDL formation is based on semi- additive processing. Therefore a Ti or TiW barrier and Cu seed layer is sputtered. Subsequently a 7μm photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4μm were achieved with high yield. In the following, Cu is simultaneously electroplated for the via contacts and interconnects traces. Finally, the photo resist is stripped and the TiW barrier and Cu seed layers are etched. The goal of the development is to provide a technology for a high- density RDL formation on large panel sizes. The paper will discuss the new developments in detail, e.g. the influence of most significant process parameters, like lithographical resolution, minimum via diameter and the placement and alignment accuracy on overall process yield.
Lars Boettcher, Group Manager
Fraunhofer IZM Berlin
Berlin, Berlin
Germany


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