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30m Thick Cu RDL and Multi-layer RDL in WLCSP
Keywords: WLCSP, RDL, Packaging
In situations where a device may have an interconnect pad arrangement in wafer level packaging, an additional layer of lateral connections may be employed to rearrange the connections in a manner suitable for wafer level processing. This additional layer is known as a redistribution layer, or RDL, and fabricated from a thin layer of metal with dielectrics in between. An RDL is used for higher electrical performance and complex routing to meet electrical requirements. As the importance of high power and power management in electronics products continue to rise, so also will the demands for power ICs to handle ever higher voltages without appreciably adding size and heat to the end product. Using thicker Cu metallization in an RDL is an ideal choice that accommodates high current density and lower resistance for high power applications. Assembling multiple chips in multiple layers requires more electrical connections, which in turn requires both thinner lines within the RDL and an increase in the number of RDL layers. The RDL line width of WLCSP started at over 20µm, but has already been reduced to 10~15µm in HVM. Industry players are now working in R&D to develop 2µm wide and even smaller line/space (L/S) capability to meet the requirements of today’s high-end applications. In this study, we present the development of 20-30m thick plated Cu RDL for high power and high current density applications. Using a plated Cu process and photo-sensitive spin-on-dielectrics materials, thick Cu RDL was achieved with the AR 1:1 design rule and the reliability assessment was carried out with JEDEC reliability test conditions. A 2-layer Cu RDL (total 6-mask process with UBM) was developed and characterized for its component and board level reliability for 5x5/7x7mm, 0.35/0.4mm ball pitch WLCSP test vehicles.
Seung Wook Yoon, DIRECTOR, GROUP TECHNOLOGY STRATEGY
JCET / STATS ChipPAC
Fremont, CA
USA


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