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Fabrication and Assembly Processes for Custom and Commercial Flip-Chip Connections to Fine Pitch Indium Bump Arrays
Keywords: Flip-Chip, Fine Pitch, Superconducting
As semiconductor technology approaches the end of Moores Law, superconducting electronics are moving forward as potential replacements or enhancements for future computing hardware. Densely populated superconducting and cryogenic systems require interconnects and interfaces that are minimized in size to reduce thermal mass, thermal leakage and to provide means to more heavily populate devices within systems. These interconnects can benefit from using superconducting structures and the ability to be implemented using small form factor interfaces, such as fine pitch In bump electrical connections. We have developed fabrication and assembly processes to implement bump electrical connections to custom and commercial interfaces onto small form factor superconducting interconnect structures. This work explored interfaces that can be bonded through the use of flip-chip techniques. The fabrication and assembly processes developed include: an In bump plating process, a bump reflow process, a flip-chip bonding process, and an under fill process (post bonding). A study was conducted to analyze the effects of compression force as it pertains to small pitch bump arrays and has been verified through successful implementation within the assembly process. Multiple compression force experiments were conducted on structures with a minimum pitch of 150 m between bumps and with In bump heights of ~ 10 m with reasonable uniformity. Details of the fabrication and assembly processes used in this work will be presented. Acknowledgement: We acknowledge financial support and technical guidance from Microsoft Research for this work.
Sherman Peek,
Auburn University
Auburn, AL
USA


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