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High-Performance, Heterogeneous IC Packaging Trends
Keywords: 3D IC, Heterogeneous Integration, Advanced Packaging Trends
High-Performance, Heterogeneous IC Packaging Trends Mike Kelly, VP, Adv Package & Technology Integration, Curtis Zwenger, VP, Adv Package & Technology Integration, Ron Huemoeller, Corporate VP, R&D, Amkor Technology, Inc. Full-reticle system on chip (SoC) die sizes, yield challenges and ultra-high-performance memory integration continue to drive heterogeneous package-level integration. SoC integration dominates the landscape, but putting large capacity, high-bandwidth memory right next to the application-specific integrated circuit (ASIC) or graphics processing unit (GPU) has created performance levels unmatched in the industry. Performance-hungry applications such as networking switches and artificial intelligence (AI)/deep learning are just some of the high-profile beneficiaries of this improvement. Also, cleaving out high-speed input/output (I/O) blocks, which do not scale well to advancing silicon nodes, and creating discrete I/O die and then re-integrating at the package level is also showing increased adoption. Based on recent improvements, choosing the right package construction for integration at the package level is an evolving task. New advances in High-Density Fan-Out (HDFO) and 2.5D through silicon via (TSV) approaches as well as evolving flip chip ball grid array (FCBGA) capabilities provide diverse solutions for this product space. This paper will explore these packaging technologies and their potential for addressing system performance requirements. © 2019, Amkor Technology, Inc. All rights reserved.
Mike Kelly, VP, Adv Package & Technology Integration
Amkor Technology, Inc.
Tempe, AZ

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