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|Electroplating Fundamentals for Coplanarity Improvement|
|Keywords: Electroplating , Coplanarity , 3D integration|
|As the definition of 3D packaging softens to include an exhaustive array of inexpensive alternatives to TSV and interposers, adjustments to processes and materials are being made to enable more and more complex 3D integration schemes. For chip stacking in SIP integration, there are at least two planarity concerns. Overall die parallelism issues lead to uneven stacks, and plated bump to bump variability across the die creates standoff issues that could result in open circuit (a short pillar) or shorting across multiple pillars in the case that solder volume or pillar height is abnormally large. Both issues can be strongly influenced by electroplating uniformity. Both potentially also create stresses in the bonded dies that drive warp and reliability failures. This fact is creating a general demand for better coplanarity for stacked dies. Measuring uniformity of plated films has a long history starting with mechanical stylus profilometers. Normal specifications for within wafer (WIW) and within die (WID) uniformity have been refined as metrology systems stepped up to full wafer measurement (all bumps) and to allow statistical calculations using huge data sets. A plated wafer may have up to 20 million pillars. As solder bumps transitioned to copper pillars, and pitches and solder volumes decreased, the possibility of pillar height variation causing failures at assembly also increased. Devices were seldom laid out with plating uniformity in mind and as issues arose, dummy features were sometimes added to aid uniform plating. While WiW and WiD uniformity are global and local versions of the same measurement respectively, the length scale difference creates dramatically different influences on each response. At the global (wafer) scale, relatively coarse (millimeter to tens of millimeter) scale uniformity of electric field drives plating rate. Note here that plating rate variations exactly correlate to uniformity variations. Plating rate is driven by current, generally governed definitively by Faraday’s Law: the amount of a substance deposited on each electrode of an electrolytic cell is directly proportional to the amount of electricity passed through the cell. The goal of chamber design in electroplating involves delivery of current in as precise a manner as necessary to create uniform deposition across the wafer. Design elements include various current distribution techniques, mass transfer, RPM, electrolyte flow control, etc. Ideally these devices allow uniform plating such that the average thickness of each die is the same, or that a similarly arranged feature on each die is the same height. If these factors are well controlled, they have little effect on the final WiD uniformity (where length scales vary across tens to hundreds of microns), and all dies across the wafer will have a similar plated thickness variation. This “residual” or intrinsic WID uniformity is governed by a variety of factors including current density, pattern geometry, bath conductivity, bath temperature, and functionality of bath additives. Ultimately, these factors govern where metal ions at the plating interface relinquish their autonomy to become part of a stable plated metal film. The combination of these factors determines the Wagner number, a quantity that describes the local current distribution uniformity. Like the term “throwing power” used in parts plating applications, a higher Wagner number indicates better plated thickness uniformity. Predicting, validating, and improving the intrinsic WID uniformity requires attention to the relationship between the plating chamber, the chemistry, and the pattern being plated. Die specific modelling of the plating system, including calculation of the Wagner number, allows prediction of the WID coplanarity. This information can be used as feedback to refine die layout or to optimize chemistry functionality to plating tool parameters to drive WID uniformity to the lowest possible value.|
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