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Semiconductor Packaging and CDM ESD Risk
Keywords: CDM, ESD, Semiconductor packaging
ESD incidents are still present among semiconductor suppliers and customers, though adequate protection from Human Body Model (HBM) ESD has been in place for many years. The most common ESD issue for semiconductor suppliers is Charged Device Model (CDM), and among customers, the ESD issues are Charged Board Event (CBE) and Cable Discharge Event (CDE). Actually, CDM, CBE, and CDE types of ESD are related. They all have to do with charge separation within the unit (packaged device, or board or cable), and a potentially damaging discharge upon metal-to-metal contact. An electric field causes charge separation within the unit, causing a very fast ramp-up discharge event due to low resistance. The culprit electric field can be from tribocharging an insulating surface of the unit or it can be an external electric field. Either way, a significant potential difference can be present across the unit, leading to a damaging ESD event. Charged Device Model (CDM) ESD sensitivity relates directly to how the device(s) are packaged. This is very different than the Human Body Model ESD, where a charged person touches metal of the sensitive unit. It is more difficult to discover and prevent CDM events. For a given electric field, the amount of charge that transfers in the discharge depends on the effective capacitance of the product, including metal leads and circuitry combined with the insulating material of the package. Electrically induced physical damage (EIPD) easily results from CDM events, leading to either unpredictable unreliability or immediate failure of the product. Various failure mechanisms are possible, depending upon which element in the device actually gets “zapped”. Tribocharging of the package is especially problematic because there could easily be thousands of volts on the insulating package. This creates a large electric field within the packaged unit, causing significant charge separation, and then discharging upon metal-to-metal contact. The ANSI-ESD S20.20 ESD control standard specifies how to keep from damaging semiconductor parts having 200V or greater CDM withstand voltages. But reports of more sensitive products coming into manufacturing are increasing, and further precautions will be necessary in the future. Not every pin or connection has the same CDM sensitivity. It is important to focus prevention and protection schemes on the most sensitive pin of the most sensitive product. Adherence to S20.20 in the workplace will prevent both tribocharging and strong electric fields near sensitive product. S20.20 requires insulators to be moved away from the work location where ESD sensitive parts may be, or to provide ionization to neutralize charge on the surfaces. If the package of the product itself could develop a charge, this must be neutralized through ionization prior to metal contact, or there will be a CDM event. CDM testing induces a predetermined voltage potential in the unit with charge separation of the mobile charges. When a grounded probe contacts a pin or solder ball of the package while the electric field is present, the test CDM discharge occurs. The effective amount of charge “buildup” in the separation of charges depends mainly on the capacitance of the package. Devices in small packages have much lower EIPD risk because of low capacitance and high “withstand voltage”. The larger the package and more complex the circuitry inside it, the larger the risk of high capacitance, hence lower withstand V. Additional issues causing more CDM risk include the fact that device protection is difficult due to the low resistance contact and very fast rise time of the discharge pulse. Also, if a product has a CDM discharge while in an external electric field and then is removed from the field, it will discharge again when contacting metal, due to a potential remaining after the previous discharge – this is termed the double jeopardy issue in CDM.
Stevan Hunter,
ON Semiconductor
Phoenix, AZ
USA


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