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High Temperature Memory Design, Implementation, and Characterization in SiC 1m CMOS Technology
Keywords: High Temperature Electronics, Memory, Silicon Carbide
Silicon carbide (SiC) is a wide bandgap semiconductor material that has shown exceptional results from 25C to relatively high temperatures (>300C) compared to standard silicon (Si) processes. The high thermal conductivity of SiC means it is superior in conducting heat more efficiently and has higher power density. Moreover, the high critical electrical field of SiC as compared to Si allows for operation at higher voltages with lower leakage currents. The ability to operate at higher temperatures, higher power densities and higher voltages make SiC highly interesting for use in harsh environment electronic systems. SiC crystallizes in over 250 different structures (polytypes), each of them having different and unique electrical characteristics. The three most commonly obtainable SiC polytypes are the cubic 3C-SiC structure along with the 4H-SiC and 6H-SiC hexagonal structures [1]. Due to commercially available wafers being 4H-SiC and fabrication issues being prevalent with other polytypes, research at the IC level has primarily been focused on the 4H-SiC polytype. High temperature environment electronics systems are in high demand in various applications such as logging-while-drilling (LWD) systems and embedded electronics which are in the core of gas turbine engine controls [2]. A major issue with high temperature operation is the exponential increase in leakage current. The lower intrinsic carrier concentration of SiC (10^-9 cm-3) in comparison with Si (10^10 cm-3) leads to lower leakage over temperature [3]. Several researchers have demonstrated analog and digital circuits designed in 4H-SiC [4]. However, a memory module is required to realize a complete electronic system in 4H-SiC that bridges the gap between data processing and data storage. Designing memory that can process massive amounts of data in harsh environments while consuming low power opens doors for future electronics. In this work, a CMOS based six transistor (6T) static random-access memory (SRAM) cell is designed and implemented in a state of the art SiC 1m twin well CMOS process. This cell consists of two CMOS inverters and two NMOS access transistors. The CMOS inverters are connected in a cross-coupled configuration and form a bistable circuit. The access transistors make or break a path between the storage latch outputs and read-write circuits by connecting them to bit lines. The cell consists of two bit lines that control the input and output of data. Cell performance is evaluated on the basis of static noise margin (SNM), leakage current, and average write power. Simulation results over a wide range of temperature (25C to 350C) yield stable values for SNM, speed, and power. Stability and cell area are the two important aspects for SRAM cell design. Cell stability is usually defined using SNM, which is the maximum DC noise voltage that can be tolerated by the cell without having any effects on the stored bit. The bit cell is most vulnerable to static noise voltage when it is in the read mode. This is due to pre-charged bit lines being connected to storage nodes, which can increase the potential of the storage nodes with a logic 0 value and cause a stored bit to flip. In order to perform a nondestructive read operation, the ratio of current driving strength for the access transistor as compared to the pull down transistor must be carefully sized to avoid the rise in the storage node with a logic 0. The ratio between the access transistor and pull down transistor is termed cell ratio (CR), which is expressed below. Cell Ratio=(W_PD⁄L_PD )/(W_AD⁄L_AD ) W_PD, L_PD, W_AD, L_AD are the widths and lengths of the pull down and access transistors, respectively. Similar to CR, there is another sizing parameter called pull up ratio (PR). This term refers to the ratio of the pull up transistor to the access transistor. The restoring strength (current driving capability) of the pull up transistor must be higher than the strength of access transistors for a cell to perform a write operation. An expression for the PR is provided below. W_PU and L_PU are the width and length of the pull up transistors, respectively. Pull Up Ratio=(W_PU⁄L_PU )/(W_AD⁄L_AD ) The designed SiC SRAM cell performance has been characterized in simulations for different values of CR (0.5,0.6,1,1.5,2,2.5) and PR (1,1.5,1.8,2,2.5,3,3.5,4,5,6) to get the most efficient cell size with optimal performance parameters. SNM values for the different combinations of CR and PR are calculated with the N-curve method and the model developed by Seevinck et al. [5]. The highest SNM is observed at CR=2.5 and PR=5, but this cell has the largest area and highest power consumption of the cell variants. Each cell variant is designed using minimum length NMOS and PMOS transistors (L=1m). The minimum width of NMOS transistors in this process is W=3m. The smallest NMOS is used in the cross coupled inverters with the increasing pull up to pull down ratio of 3:1 to 8:1. Simulation results show a SNM of 4.08V at 300C, with a read static noise margin (RSNM) of 1.68V for CR of 1.5 and PR of 2. Simulation results at room temperature yield a current consumption of less than 1 mA for a supply voltage of 15V. With increasing temperature, current consumption increases to the milliamps range. The fabrication of the cell is in progress at the time of this abstract submission and is expected to be completed by February 2019. The final paper will include the measured results with an in depth analysis of SNM, leakage current, and average write power. This paper validates the need and sets the foundation for monolithic SiC ICs that can operate reliably in extreme environment conditions.
Affan Abbasi,
University of Arkansas
Fayetteville, Arkansas
United States

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