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|Contact Electroplating Technology (CET)|
|Keywords: flexible electronics, printing, surface finishing|
|Contact Electroplating Technology (CET) By Dr. Igor Kadija, ECSI Fibrotools, Inc. ABSTRACT The-state-of-the-art electroplating processes in electronics rely entirely on making direct contact of the power supply to the electroplated part. This is done either by having a heavier gauge clamp attached to one end of the object to be plated or with a, sometime intricate, conductive path or seed layer capable of delivering adequate polarization to the electroplated parts of the pattern 1,3,6,9,11,12. In most instances that type of direct link to the power supply presents a nuisance, forcing the designer of electronics to cope with the introduction of non- functional parts, such as seed layers, taking space from the precious real- estate of the electronic substrate. At the end, these sections of the substrate may be either kept or removed from the final product. There are numerous industrial applications where metallizing of isolated electronic structures is necessary in order to deliver a viable product. Some examples are flexible electronics, PCB surface finishing and IC manufacturing. The typical state-of- the-art approach by the industry is to apply electroless processing or by application of metal containing pastes, both burdened with inherent problems. The electroless process involves handling of specialty chemicals that require maintenance and costly disposal to minimize the environmental impact. In addition, the process itself is quite slow5, typically 10-50 times slower then electroplating, requiring long process time while delivering deposit of lower purity and density then its electroplated counterpart. In flexible electronics processing the metal paste comes with its inherent deficiencies, such as requiring thick deposits followed by curing step, at the end delivering an inferior product. IC fabrication calls for iterations of Chemical Mechanical Polishing (CMP) application in order to eliminate seed layer and excess Cu plating between the IC interconnects12-15, the only way ICís can be produced. It is desirable to have an efficient way for establishing the contact between the substrate and the power supply, to enable the electroplating process without sacrificing the substrate real estate. For several decades efforts to electroplate isolated features have been made in the past, including the authorís and others7,8,10,14,15,16. None of these resulted in an efficient and practical solution. More recently a novel and potentially practical approach17,18 is being made by ECSI Fibrotools. The process is the subject of this article. By applying the Contact Electroplating Technology (CET) with up to several million electrical contacts per square inch, each isolated structure is simultaneously contacted and charged by the main power supply via the CETís working electrode. CET technique has been demonstrated with actual patterned structures of various substrates such as flexible electronics, PWBs finishing and various small electronic devices. For example, in flexible electronics, following a high-speed xeroxing or patterning of isolated electronic structures with a seed layer of negligible thickness, the CET technology enables upgrading of the same by deposition of pure metal of desired thickness up to 10 microns. Electroplating occurs directly on thin seed layer or toner enabling well- defined metal plating. Completely isolated electronic interconnects were uniformly electroplated for surface finishing with Ag and Cu. Some examples of needed future optimizations as well as some competing technologies follow. For CET application the selection of initial patterning technique of polymer sheet for flexible electronics is a challenge. What kind of efficient and simple seed layer pattern printing technique would complement CET application? Possibly, a variety of options can be considered as CET technique works with seed layers with resistances up to 1 kilo ohm cm. Furthermore, in surface finishing implementation, while offering huge savings in environmental protection, CET still needs to identify the optimal combination of the sandwich structure for overcoming relief irregularities of certain group of PCBs. What combination of FC/M and electrolyte carrying material would provide the adequate flexibility to adapt to the substrate relief while processing? Several combinations may end up being prepared for specific applications. The CET process is competing with a rush of developments specifically in the field of flexible electronics and IoTs. More specifically, conductive textiles19, 20 are having wide spread usage. However, in addition to inferior conductivity, the reel to reel processing appears to be out of reach. The stretchable textile materials do not seem to lead to an efficient and controllable process for introducing metalized fibers with precision to isolated conductive sites. Thus, thin polymer substrate such as milar used in flexible electronics applications is still predominantly patterned with metal pastes utilizing the laser or screen-printing technique. Graphene technology21, 22 is maturing rapidly. While it is been touted as a material for universal application it is still struggling with an inherent excessive surface resistance to enable more universal electronic application for interconnect usage. Vader Systems23 of 3D printing molten metal technology is making significant breakthroughs in fabrication. Still, production of high- density electronic devices involving molten metal application on, in many practical instances only several hundred microns thick polymer materials, may be a serious obstacle. Furthermore, most of the PWB patterned structures are not accessible to jet coating over the sidewalls. This limits application of liquid metal jet printing technique. In contrast, PWB surface coating with electroplated metal by applying the CET process appears to be a viable technique. Keywords: flexible electronics, electroplating, printing, surface finishing, IC fabrication|
|Igor Kadija, President & CEO
ECSI Fibrotools, Inc.