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Here is the abstract you requested from the imaps_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Study to Lower Cu Pillar Flip-Chip Failure Rate
Keywords: Cu pillar flip-chip , modeling, PPM failure rate
Cu pillar flip-chip die technology has proved reliable and widely used in chip to package mobile module products. There was a time when customers considered 500PPM (Parts per million) an acceptable defect rate. Now, tier 1 customers expect a defect rate of less than 50PPM. This high customer expectation droved this in-depth research. Our research mainly includes 1) Mapping and analyzing initial defects. 2) Developing an effective way to detect a low defect rate. 3) 3D mechanical modeling that focuses on multiple failure interfaces and modes. 4) Simulating stress factors and their impacts. 5) Verifying hypothesis with assembly design of experiment (DOE). 6) Proposing advanced design rules and processes for improvements. This paper summarized our research results, provided data analysis and directions for further improvements to lower Cu pillar die defect rate.
Shannon Pan, product pacakge engineer
Qorvo
Greensboro, NC
USA


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