Abstract Preview

Here is the abstract you requested from the imaps_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Nano void Formation at Cu/Cu/Cu Interconnections of Blind Micro Vias: A Field Study
Keywords: Blind Micro Via, reliability, Nano void
The electrical reliability of multilayer HDI/BGA-PCBs is mainly affected by the thermo-mechanical stability of stacked micro via interconnections. Here, a critical failure mode is the stress related crack between the electrolytically filled via and the target pad, commonly known as target pad separation. The junction includes two Cu-Cu-interfaces, one between the target Cu pad and the thin electroless Cu layer and the second between electroless Cu and electrolytic Cu. Large nano-voids (with dimensions of several ten to several hundred nm) and inhibited Cu recrystallization across the interfaces are the two main indications of a weak link to the target pad, and are well observable via standard inspection tools such as FIB/SEM*. Recently, closer inspections of such junctions were performed via transmission electron microscopy (TEM) and a substantial density (up to 30000 voids/µm3) of circular shaped small nano-voids with diameters below 10 nm were observed [1][2]. The Nano-voided regions were assigned to the electroless Cu layer. To evaluate the impact on the junction reliability and to find probable root causes of this newly discovered void-phenomenon, an extensive field study of more than 400 TEM investigations, incl. TEM-lamella preparation, HAADF-TEM, XEDS and EELS-measurements*, was performed. TEM in combination with XEDS enables the localization of the electroless Cu layer in the junction by detecting the codeposited Ni (typ.: 0.2-1.5 at%) and a precise assignment of the nano-void affected interfaces or layers. This nano-void field study comprised the investigation of HDI and BGA-multilayer PCBs with stacked vias produced by several industry partners and single layer reliability test boards produced in industry like on-site facilities (Atotech Techcenters), accompanied by some laboratory plating tests. Different types of industrially relevant electroless Cu pretreatments, Pd-activator systems, electroless Cu baths and filling Cu-electrolytes were included in the test matrix, as well as the impact of a subsequent thermal treatment (one to ten IR-reflow cycles). In this paper we will discuss the following main results of this field study, with regards to root causes and probable failure mechanisms: • Two types of nano-voids are identified o Thermally induced nano-voids which are not visible immediately after electroplating and only become apparent after additional thermal treatment. o Plating induced nano-voids, that are visible immediately after electrolytic plating and do not form as a result of additional heat treatment. • For thermally induced nano-voids – The tested electroless Cu pretreatments and varying amount of adsorbed Pd by different Pd-activator systems have no direct impact on nano-void formation. Interestingly, the adsorption of Pd-nanoclusters (50-100nm diameter) on the target pad of a BMV, e.g. from Pd precipitations in the activator solution, causes the formation of both small and large nano-voids. • For plating induced nano-voids – The type of electroless Cu, i.e. the used stabilizer system, is the main impact factor on nano-void formation at the target pad/electroless Cu interface. This void-type is observable without subsequent thermal treatments • The absence of nano-voids in the electroless Cu layer on top of the Cu-clad panel (capture pad) compared to the high void-density at the BMV-bottom (target pad), points to Cu-depletion as an prerequisite condition to trigger the nano-void phenomenon in BMVs. • Nano-void formation close to the electroless Cu/electrolytic Cu interface is related to the combination of the stabilizer system of the electroless Cu and the type of electrolytic Cu, e.g. the type of used Leveler system. A suited combination of electroless and electrolytic Cu is able to produce a completely nano-void free Cu/Cu/Cu-junction. • Despite a substantial higher nanovoid-density in case of eless Cu type A compared to eless Cu type C, both electroless Cu baths examined show comparable and acceptable reliability performance through standardized thermal cycling test and quick via pull tests. *TEM-Transmission Electron Microscopy, HAADF-High Angular Annular Dark Field mode of TEM, XEDS-X-Ray Energy Dispersive Spectroscopy, EELS-Electron Energy Loss Spectroscopy
Tobias Bernhard, Scientist R&D
Atotech Deutschland GmbH
Berlin, Berlin

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Rochester Electronics
  • Specialty Coating Systems
  • Spectrum Semiconductor Materials
  • Technic