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|Improve Control amidst Die Shrink, 3D Package Complications|
|Keywords: FOWLP, Bump metrology, Advanced packaging|
|Consumer tolerance for device failure is at an all-time low, as they demand more functionality and more convenience from their electronic devices. The demand for higher performance electronics in smaller packages has led to the development of wafer level packaging (WLP), panel level packaging (PLP) and fan-out level packaging. All of these advanced packaging techniques involve extensive use of bumps to establish electrical connections in vertical directions. Packaging these vertically-integrated dies requires the need to provide interlayer connections that are as small and reliable as the multilayer interconnect technologies used within the chip. This need for vertical connections has created a whole new class of technologies advanced packaging with a whole new lexicon of terms and acronyms: through-silicon vias (TSVs), redistribution layers (RDLs), bumps, pillars, nails, under bump metallization (UBM), wafer-level packaging (WFP), fan-in, fan-out, and many more. All these technologies serve the purpose of providing reliable, electrically isolated, vertical connections, and most, at some point, involve the creation of a conductive bump protruding through an insulating layer to carry the signal to the next layer above or below. Die sizes continue to shrink and packaging technologies continue to evolve, but the common thread for all of them is the need for increased precision and tighter process control limits to achieve final package yield. Nearly all packaging technologies require connections in the third dimension, above or below the die, thus adding, quite literally, a new dimension to inspection and metrology requirements. Increased focus on reliability for automotive, health care and even mobile electronics is driving the need for improved process control solutions. The combination of higher packaging complexity and the need for improved reliability are driving changes to the requirements around inspection and metrology. Vertical integration continues to grow at a pervasive rate and the need for improved process control in the third dimension is growing rapidly in order to ensure reliability. Vertical integration is designed into nearly all packaging forms, including TSV, RDL, WLP, Fan-in, Fan-out, with a focus on continued increase in the number of I/Os, the pitch of features (RDL and bump) and the overall package size increasing. This integration drives the need for 3D metrology of feature height and coplanarity. In addition, the need to augment raw 3D metrology with defect inspection and 2D metrology data enables a comprehensive view (insight) into the packaging process. Achieve total bump process control with the combination of data from: (1) 2D defect detection voids and shorts, foreign material, misprocessing; (2) 2D metrology bump diameter, bump position, bump presence; (3) 3D inspection bump too tall, bump too short, statistical process control (SPC); (4) Auto classifications data must make sense and be easy to interpret. By combining high speed 2D, 3D metrology with defect inspection and advanced analytics, the quality of process control data can be exponentially improved to enable quick time-to-results for both process development and HVM control. This paper describes the inspection and metrology challenges of bumps in advanced packaging and the next generation high-throughput bump inspection methodology for wafers with extremely high bump counts as well as the data analysis|
|Woo Young Han, Senior Applications Engineer