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|Development of Backside Buried Metal Layer Technology for 3D-Ics|
|Keywords: 3D IC, Backside Buried Metal Layer, PDN|
|Three-dimensional integrated circuit (3D-IC) technology with through-silicon vias (TSVs) [1�5] is a very effective method for producing advanced, high-speed, compact, and highly functional electronic systems. However, stacking multiple chips can cause power integrity issues with respect to circuit design. For example, large simultaneous switching noise (SSN) is generated when stacked chips are switched simultaneously. This SSN can generate unpredictable voltage noises in the power delivery network (PDN) and cause system failure. In order to solve this problem, the impedance of the PDN must be reduced. Two methods were proposed in a previous study. The first method  is that decoupling capacitor chips are placed on a printed circuit board or a package, but the effectiveness of this method is insufficient in high frequency region because the distance between the decoupling capacitor chip and the 3D-IC is large. The other method  is that MIM capacitors and MOS capacitors are formed in frontside of the IC chip as the decoupling capacitor. In this method, since the capacitor is formed in the circuit region, its area cannot be increased much, and the circuit design is restricted. In this study, the backside buried metal (BBM) layer technology is proposed to reduce PDN impedances and improve power integrities of 3D-IC circuits. With this technology, a BBM layer for global power routing is introduced in the large vacant area on the backside of each chip and is parallelly connected with the frontside routing of the chip. The resistances of the power supply (VDD) and ground (VSS) lines consequently decrease. In addition, the BBM structure acts as a decoupling capacitor because it is buried in the Si substrate and metal�insulator�silicon structure. Therefore, PDN impedance can be reduced by introducing the BBM layer. Further, a simple yet novel process was developed, which is fully compatible with a via-last TSV process for forming the BBM layer. This process primarily consists of seven steps: (1) wafer thinning, (2) deep-Si etching for TSV formation, (3) trench-Si etching for BBM formation, (4) etching of bottom SiO2 layer, (5) low-temperature chemical vapor deposition for isolation between TSV (BBM) and Si substrate, (6) etchback and cleaning to remove the insulator from the bottom of the TSV and form an electrical contact between the TSV and first metal layer, and (7) metal filling and chemical mechanical polishing. With this process, it was possible to fabricate the BBM layer consisting of electroplated Cu (width: 15 um, thickness: 10�20 um) buried in the backside of the CMOS chip (thickness: 40 �m), which was connected with the frontside routing of the chip by TSVs of 10 um-diameter. In addition, the TSVs and BBM formed in this process showed good electrical performance. The resistance of a 10 �m diameter TSV was approximately 50 m ohm, and that of the BBM of 20 um width and 200 um length was 23 m ohm. This BBM layer technology is expected to improve the power integrity and contribute to overall performance enhancement of 3D-ICs.|
National Institute of Advanced Industrial Science and Technology (AIST)