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Advanced Die Saw Technology for WLCSP Reliability Enhancement
Keywords: WLCSP, Die Saw, Plasma
As consumer and portable devices get thinner and more functionality. Chips which are made by less than 28nm node wafer with extreme Low-k (ELK) inter metal dielectric material is a trend in order to contain more transistors and to lower power consumption. However, side wall crack (SWC) for WLCSP is one of the major challenges since ELK layer getting brittle. Laser grooving (LG) is applied to remove metal before blade saw, but the high temperature during laser grooving usually easily generates HAZ (heat- affected zone) which can induce stress concentration and lower chip strength. The laser ablation also leaves silicon residue (or recast) from the re- deposition of silicon to the groove and surrounding areas. Therefore, SWC (sidewall crack) is a huge potential risk waiting to happen after pick/place , during shipment and during SMT process. In the industry, HAZ size and SWC rate could be reduced by adjusting process parameters, or by exploring new alternatives to eliminate HAZ and silicon recast are one of driving factors of this paper. In this study, plasma etching was applied as surface treatment on the scribe line after laser grooving process with ELK wafer. Plasma could etch HAZ and recast area and expected to increase chip strength and reduce SWC rate. Plasma applied with various process time and power, and different types of LG coating materials were studied. Different plasma gases and effectiveness will be discussed. Conventional blade dicing process will be compared to different plasma etching conditions for mechanical properties of die using 3 point bending to check die strength, and CSAM and IR scan check to verify quality of sidewall of the die. Finally drop test is performed to confirm the reliability enhancement.
Ching Chia Chen, Senior Engineer
Siliconware Precision Industries Co., Ltd.
Taichung , Taiwan

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