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Package Qualification Envelope for 22FDX® Technology
Keywords: Chip-Package Interaction (CPI), 22FDX® Technology, Package Qualification
ABSTRACT With 22FDX® technology, GLOBALFOUNDRIES has introduced a new semiconductor node to meet the ultra-low power requirements of the next generation of connected devices. This technology platform delivers FinFET-like performance with an energy efficiency that is cost comparable to 28nm planar technologies, providing an optimal solution for the rapidly evolving mainstream mobile, Internet-of-Things (IOT), RF connectivity and networking markets. In order to address the different market segments for the 22FDX® technology multiple Backend of Line (BEoL) stacks and package configurations including wire bond, flip-chip CSP, wafer level Fan-In and Fan-Out had been qualified with respect to package and board level reliability. The paper describes the criteria for the selection of BEoL stacks, die and package sizes and interconnect material used for the qualifications. Furthermore, the paper discusses the purpose, the specification and placement of the Chip Package Interaction (CPI) test structures implemented on the test qualification vehicles (TQV) for each package configuration. The general qualification approach includes the collection of materials characterization data of unstructured films, the characterization of the BEoL stack integrity by Dual-Cantilever Beam (DCB) test, Modified Edge Lift-off Test (MELT) and Bump Assisted BEoL Stability Indentation (BABSI) tests, an early reliability assessment and the qualification on the package level. The paper describes the methodology to generate BEoL strength data on wafer level with a complete metallization stack assessing the crack stop strength and BEoL integrity. Dedicated CPI test vehicles have been designed for component level reliability assessment. Various types of CPI sensor structures have been implemented on these TQVs to verify the integrity of the die seal, the integrity of the BEoL stack under the bumps and the wire bonding pads, as well as the integrity of the Cu Pillar interconnect. The correlation between CPI data collected on the wafer and package level will be shown and discussed. Technical challenges and solutions with respect to Cu Pillar bumping and assembly processes will be discussed. The paper describes the Cu Pillar bump design rules and process improvements to address assembly challenges. Finally, the paper presents results showing the influence of these assembly technologies on 22FDX® package reliability. The data set includes results of pre-conditioning, temperature cycling (TC), unbiased Highly Accelerated Temperature and Humidity Stress Test (uHAST) and High Temperature Storage (HTS) data for flip-chip and wire bond qualifications. Furthermore, a comparison of reliability data on component and board level for wafer level Fan-In and Fan-out will be provided.
Frank Kuechenmeister, Principal Member of Technical Staff
Dresden, Saxony

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