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|Low-Density Fan-Out Heterogeneous Integration of MEMS Tunable Capacitor and RF SOI Switch|
|Keywords: MEMS, RF, LDFO|
|Microelectromechanical systems (MEMS) sensors and devices benefit immensely from the rapid development of advanced packaging technologies and, in particular, the ability to integrate dissimilar components within a single package. Device-to-device interconnect parasitics are a major concern in radio frequency (RF) applications and are further exacerbated by traditional discrete integration techniques on the printed circuit board (PCB). Low-Density Fan-Out (LDFO) also known as Wafer-Level Fan-Out (WLFO) packaging provides the ability to create a reconstituted wafer comprised of one or more original foundry silicon technologies, on which standard wafer-level packaging processes can be carried out. Leveraging the fine line and space capabilities of wafer-level lithography, device-to-device interconnect complexity can be greatly reduced resulting in low parasitics and improved RF metrics such as self-resonance frequency (SRF) and quality factor (Q). Apart from the performance benefits of multi-die integration are the reduction in packaging costs and substantial space savings as compared to a discrete implementation, which is attractive for handset and non-handset wireless markets alike. Using LDFO packaging technology, an RF MEMS tunable capacitor array comprised of electrostatically actuated beams on 180nm CMOS silicon  was heterogeneously integrated with a single-pole four-terminal (SP4T) RF switch on 180nm CMOS silicon-on-insulator (SOI). In addition to the primary intent of more versatile switching between capacitive states, the RF switch also serves as high voltage electrostatic discharge (ESD) protection for the MEMS device. The objective of this study is two-fold: to determine the manufacturability of a multi-chip MEMS device through the LDFO packaging process and prove through RF and ESD characterization that the package is not only comparable to existing packaging solutions , but also provides a notable improvement over discrete PCB integration. Manufacturability is proven at time zero through survival of the MEMS device based on hermeticity of the individual electrostatic beam cavities as well as their open and closed state capacitance values. RF characterization metrics include SRF, Q, harmonics and linearity of the device at time zero. A previous study indicated acceptable manufacturability and performance of the RF MEMS tunable capacitor array by itself through the LDFO (WLFO) packaging process , most notably the ability of the electrostatic beam structures and their respective hermetic cavities to survive the thermo-mechanical stresses involved with over-molding, polymer curing, etc. Capacitive MEMS structures can be particularly sensitive to unpredictable electrostatic charging scenarios such as handling after package assembly and PCB surface mount processing. Consequently, resistance to dielectric breakdown by means of robust ESD protection is a very desirable quality. Integrating the RF switch in close proximity with the MEMS device not only provides the ability to withstand charging scenarios in excess of 1kV (human body model), it mitigates the impact of parasitics on RF performance by minimizing interconnect lengths and complexity. The progression of LDFO heterogeneous integration could eventually obviate the need for a System-on-Chip (SoC) approach by providing two-dimensional interconnect dimensions comparable to sub-micron wafer foundry processes. This would allow for greater flexibility in chip design with lower upfront costs and, ultimately, a shorter time to market. These benefits would have a substantial economic impact on the cost per sensor, furthering the ubiquity of MEMS in microelectronics applications. © 2019, WiSpry, Inc. All rights reserved. © 2019, Amkor Technology, Inc. All rights reserved.|
|Rameen Hadizadeh, Packaging Technology Manager