Abstract Preview

Here is the abstract you requested from the imaps_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Bumping Co-planarity Collocation for Different UBM Size by Geometry Integration
Keywords: Co-planarity, Cu Pillar Bump, Solder Cap
Bumping co-planarity is a key index of plating Cu pillar bump, which may impact to the joint quality of following flip chip bonding process. The minor the co-planarity value represents the minor variation of the plating bump height. Better co- planarity can be controlled by bumping process, however some of the designs cannot be covered by process control, for example dummy bump or structure drawback. This paper provides a methodology by integrating the solder volume of different bump shape, by collocate the oval bump & circular bump, the co-planarity can be improved. Due to the geometry variance from the oval shape and circular shape, the final solder formation is different. The final solder height can be calculated by mathematical integral from as-plating solder volume, it can be predictable. Hence, better co- planarity can be derived by the method of different bump shape collocation. The predicted collocation rule can derive the optimized co-planarity result, which can be designed at day1 to prevent poor quality.
Wei-Wei (Xenia) Liu, Section Manager
ASE Group
Taoyuan, Taiwan

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Rochester Electronics
  • Specialty Coating Systems
  • Spectrum Semiconductor Materials
  • Technic