Abstract Preview

Here is the abstract you requested from the imaps_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Understanding the Effects of Process Parameters to Compensate for Substrate Warpage in Chip on Flex (COF) Assembly Using Conventional Reflow
Keywords: Chip on Flex (CoP), Mass Reflow, Warpage
Mounting large silicon chips on a flexible substrate presents a unique set of challenges. Surface flatness and warpage during thermal processing being two of the biggest issues. Different methods for chip on flex (CoF) assembly have been proposed in the literature which include use of metal frames to mount the flexible substrate [1], using vacuum fixture to keep the substrate flat during pick and place operation and thermal processing [2] as well as in-situ bonding or anisotropic conductive films (ACF) [3, 4]. However, these methods are either not very practical for high volume mass production or compromise the through-put of the assembly process. In this work we will be presenting preliminary results from our ongoing research to develop a high yielding CoF assembly process that uses standard mass reflow process, equipment and materials, which will be suitable for high volume mass production. Yield for this study has been defined as the ratio of number of good electrical connections to the number of total intended connections. A 17.50 mm X 6.75 mm silicon die with a 32 X 8 array of solder bump/Cu pillar interconnects with a pitch of 0.8 mm has been used for this study. The flexible substrate used is a two-layer polyimide substrate. A fixture that makes use of a flat metal plate with magnets and a metal window frame with openings for the silicon chips that sits on the metal plate was used to keep the flexible substrate flat during solder reflow. Different stencil aperture openings were used to print solder on solder pads to understand if it can compensate for lack of substrate flatness and substrate movement during reflow. A comparative study was done using both solder bumps and Cu pillars as interconnects. Further, process yield was calculated for placement force of 150 mg and 300 mg during the pick and place operation. Hence using aperture diameter, interconnect type and placement force as the three variables, a 23 full factorial experiment was designed. Along with yield of the process, the stand-off height was also calculated for each leg of the experiment as it is well documented that increase in stand-off height results in reduction of thermal stresses at interconnect locations due to coefficient of thermal expansion (CTE) mismatch [5]. A higher stand-off height also helps in flux cleaning operation post solder reflow. Finally, thermal simulation using finite element analysis (FEA) was performed to calculate stresses during thermal cycling between the expected temperature range to which the assembly will be subjected. References: [1] Varun Soman, Mark D. Poliks, James N. Turner, Mark Schadt, Michael Shay, and Frank Egitto.
Varun Soman,
Binghamton University
Methuen, MA

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Rochester Electronics
  • Specialty Coating Systems
  • Spectrum Semiconductor Materials
  • Technic