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|A Novel Fabrication Process for High Density Silicon Capacitors by using Metal-Assisted Chemical Etching|
|Keywords: Metal-assisted chemical etching, Silicon capacitors, High aspect ratio trenches|
|Silicon capacitors have been commonly used in power supply systems and high frequency circuit equipment over the past decade. However, due to the limited capacitance and high cost of silicon capacitors, the applications are still remained improvable. In silicon capacitors, it is most important to increase the surface area of the surface forming the capacitor. In conventional silicon capacitors, trenches are generally formed in silicon wafer using reactive ion etching (RIE) method to expand their surface area. However, with this method, the depth of trenches that can be formed was limited. Furthermore, since RIE method processes silicon wafer only one by one, productivity is low. In this paper, Metal- assisted Chemical Etching (MacEtch) is proposed as a novel method of fabricating high-density silicon capacitors to solve the problems. The MacEtch technique is a catalytic wet etching method that using a noble metal catalyst. In briefly, the catalyst layer is deposited on a silicon wafer, and which is then immersed into an etchant consisting of an oxidant and a hydrofluoric acid (HF). The catalysts activate the oxidation action of the silicon atoms under the etchant. Therefore, the silicon atoms near by the catalysts are selectively eroded, so the silicon wafer can be etched corresponding to the pattern of the catalyst layer [1- 5]. The mechanism of the MacEtch and the suggested conditions for making high aspect ratio vertical trenches are discussed. It was found that the verticality of the trenches could be controlled by the conditions of the catalyst and the etchant composition. Since MacEtch can be understood as a galvanic reaction with a catalyst as a cathode and silicon as an anode, the shape and amount of the catalyst affects the etching rate and the verticality of the trenches, in particular. We used gold formed by electroless plating as a catalyst and controlled them by forming conditions. As a result, vertical trenches with a greater than 100 ƒÊm depth and less than 1 ƒÊm width on a silicon wafer could be formed. The silicon wafer on which these trenches are formed has a surface area of 100 times or more as compared with the case where there is no trench. We formed a dielectric film and electrodes on these trench surfaces. Consequently, we have been realized a silicon capacitors with a capacitance density as high as 200 nF / mm2 or more.|
|Susumu Obata, Senior Research Scientist