KemLab

Abstract Preview

Here is the abstract you requested from the imaps_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

A Study of Defects in High Reliability Die Sort Applications
Keywords: Sort, Inspection, Traceability
As the traditional semiconductor device processing techniques are used for device fabrication and packaging in a growing number of industries with high reliability requirements such as aerospace, automotive, defense, and medical, the importance of ensuring only known good devices are used at each packaging step becomes more critical. The concern for device quality is magnified when considering that these new devices push the boundaries of existing back-end semiconductor processing equipment, whether due to device size, thickness, surface features, or material properties. This can lead to a greater incidence of defects during the post-dicing die sort process. Any defects passed through the die sort process can create further downstream issues including customer concerns with quality/reliability, increased costs through rework or scrapping of a package with defective device, and premature end product failure. While quality remains a key concern in high volume manufacturing, it is critical in low volume, high mix environments such as research and development or prototype laboratories or die sort service providers. This paper will survey several categories high risk die sort applications to understand defects caused during the singulation (dicing) process, defects that can be caused during the die sort process based on the die handling method used, and defects that must be detected at this stage before proceeding to the next processing step. In each category we will sort parts using an in-line automated visual inspection of die top surface and edge in order to confirm the success of the evaluated die sort method for not inducing defects on the parts, the strengths and weaknesses of each handling approach, and which defects and cannot be detected at this processing stage. The applications that will be considered will be first MEMS devices requiring a die handling approach with non-surface contact (and no vacuum contact) to protect the delicate structures on the MEMs device surface such as cantilevers, membranes, and resonators (Zaal 3989). Use of a non-surface contact edge grip process will be considered and compared to a collet or radius style vacuum pick-up approach. Any damage to these structures must be prevented and screened for, along with any foreign particulate matter which can get stuck in the surface structures. Next thin die used for RF and microwave applications such as MMIC devices requiring delicate handling due to thin nature and three five material make-up will be considered. For these parts design of packed needle array eject head and pick-up tool to support the die during the die eject process is evaluated, and then device must be screen for micro-cracks on device edges to ensure success of tooling design. 50 and 100 micron thick devices will be considered. Top surface visual inspection of these devices can also screen for visual defects in vias, bond pads, etc. The role of flexure based pick-up head design will also be compared with non-flexure based pick-up design to evaluate which provides most delicate handling approach for thin fragile die by visual surface inspection after the die pick. Finally, optoelectronic and photonic devices will be considered. For these devices the key constraint, similar to MEMs devices, is to eliminate surface contamination of the devices, with specific focus on any particulate matter in the emitting areas of the chip (i.e. the facets of edge emitting communications laser diodes), which can cause thermal control issues leading to device performance issues (Chen & Gerke 299). To this end both surface contact and non-surface contact handling approaches will be evaluated, as well as the challenge of inspection transparent die surfaces. In each of the presented applications, a successful pick and place process was able to be designed and verified using in line inspection for defects, as well as used to continually monitor and provide process control and traceability to ensure only known good devices in each of these processes are delivered to next step of the production process. By logging the process information (Wafer ID, Lot ID, and Product ID, wafer coordinates – map location), along with the inspection results and images, and die placement location on the output including Tray ID, a quality record is provided demonstrating a high reliability die sorting application even for the most challenging processes.
Sarah Parrish, Sr. Sales Applications Engineer
Royce Instruments
Napa, CA
USA


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Rochester Electronics
  • Specialty Coating Systems
  • Spectrum Semiconductor Materials
  • Technic