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FOWLP / FOPLP lithography solutions to overcome die placement error, predict yield, increase throughput and reduced cost.
Keywords: Panel, Yield, Productivity
The Internet Of Things (IOT), mobile, memory and automotive applications are major market drivers. These drivers require high performance, low cost, increased functionality and reliability (especial for automotive) 2.5D and 3D packaging solutions. Fan Out Panel Level Packaging (FOPLP) is one of the technologies that has the potential to meet these packaging requirements. FOPLP processes require the reconstitution of dies on a substrate, which are displaced from their nominal grid location during the epoxy molding compound process. This fan out technology delivers more space for redistributed I/O connections, providing more flexibility for homogeneous and heterogeneous integration. Moreover, the final package size can be increased since the panel format supports more packages per substrate than wafers. Although FOPLP processing has many advantages, it also faces significant challenges. One critical challenge is the reconstituted die placement error, which occurs during the reconstitution and molding process. These placement errors are amplified with the larger panel format when compared to reconstituted wafers, and errors of 50um or more are not unusual. In order to guarantee acceptable yield, these errors must be corrected during the lithography process using site by site corrections. This process is time consuming when using site by site alignment or metrology on the lithography system. Substrate alignment and error correction are traditionally calculated using global alignment, but this does not accommodate the non-linear die placement errors. It is clear that only site corrections can deliver the overlay required to maintain good yield. Typically, this approach has a huge impact on throughput and would increase the cost of FOPLP process making it impractical. In this paper we demonstrate a revolutionary FOPLP lithography solution for the die placement error challenge. We describe the use of an external metrology tool to capture die placement error data from a wafer or a panel, and a “feed forward” solution to optimize stepper, site by site, X, Y and rotation offsets, during exposure. We also show how visualization of the metrology data provides the user with the ability to characterize upstream and downstream processes together with a unique yield predication capability. This revolutionary solution significantly increases stepper throughput, reducing cost and increasing productivity at the same time ensuring high yield.
Keith Best, Director Applications Engineering
Rudolph Technologies
Wilmington, Massachusetts
USA


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