Here is the abstract you requested from the imaps_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Cu pillar bump development for 7nm Chip package interaction (CPI) technology qualification|
|Keywords: 7nm technology, chip package interaction, Cu pillar bump|
|Abstract The power, performance and area gains are an important metric which drive the technology from older nodes to new ones. The steady down-scaling of feature sizes of the CMOS technology has been the leading force for the continual improvement in circuit speed and cost per functionality over the past several decades. The increase in functionality which needs a larger number of signal I/O's in combination with small die size requirements as a result of transistor size reductions have driven the reduction of the bump pitch. For 7nm, 130um becomes the common pitch for high performance devices. With the pitch reduction, conventional sold bump can’t be used for 7nm technology. Cu pillar bump is the best candidate for smaller bump pitch. But Cu pillar bump will induce higher stress to the Si and cause ELK crack to affect chip package interaction reliability due to the CTE mismatch between Si and substrate. Cu pillar bump has been developed for 7nm technology. The reliability of Chip package interaction with Cu pillar bump is very critical. In this paper, simulation has been used to assess the stress on ELK with the Cu pillar dimensions like UBM size, PI opening, Cu pillar height, solder cap height, min bump pitch, terminal pad thickness, terminal metal diameter to select the POR parameters of Cu pillar. A TV with die size of 460mm2 and 7nm BEOL has been designed and made by 7nm process technology and used for the 7nm CPI technology qualification. Assembly process has been developed and optimized. Accelerate thermal cycling test was used to evaluate Cu pillar bump effect on the ELK cracking. The reliability test to follow Jedec standards have been followed to qualified Cu pillar bump CPI for 7nm technology. EM test showed much better performance than SnAg bump. The Cu pillar bump technology qual passed for the 7nm technology and implement on 7nm production.|