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A Low Inductances Full SiC Power Module Based On a Novel Stacked Multi-DBCs Hybrid Packaging Structure
Keywords: SiC power module, stacked DBCs packaging, low parasitic inductance
Compared to silicon devices, SiC devices have lower Coss and Qg, so SiC devices can achieve higher switching speeds, resulting in higher dv/dt and di/dt during switching [1]. The high switching speed enables low switching losses and high switching frequency, which can increases converter power density and efficiency [2]-[3]. However, at high switching speeds, higher di/dt will result in higher voltage overshoot and ringing on the device, which increases device switching losses, device voltage stress, and EMI noise [4]. However, commercial SiC modules are typically based on traditional two- dimensional wire bonding techniques with approximately 15 to 30 nH parasitic inductance. Large parasitic inductances do not take full advantage of the high switching speed of SiC devices, so it is necessary to reduce the parasitic inductance of the module by optimizing the package design. Hybrid package structure has the potential to reduce parasitic parameters. This structure can achieve a multi-layer 3D power loop structure with wire-bonding and stacked multi-substrates [5]-[6]. This structure has simple manufacture processes and higher reliability. Z. Chen [6] uses DBC and PCB stacked forming a multilayer structure. But the proposed structure DBC+PCB stacked hybrid structure still has large the common source inductance, and power loop mutual cancellation is not well designed. Furthermore, the current rating is limited by the PCB copper tracer. Therefore, some stacked DBCs based hybrid structures are developed [7]-[8], which have high current capability and better thermal performance. Therefore, a hybrid packaging structure based stacked DBCs power module with low loop inductance and terminal inductance will be proposed in this paper. The 3D power loop of one HB-cell is optimized based on the stacked DBCs, which has 4.3 nH power loop inductance and nearly zero common source inductance. In addition, a parallel multi-chip power module with symmetric current distribution is introduced. The power loop inductance of this module is 1.8 nH and the low profile terminal with laminated busbar structure is 1.7 nH. The terminal inductance influence for multi-chip parallel current sharing is analyzed. The distributed symmetrical terminal structure and decoupling capacitor integrated can improve the current sharing. Additionally, the high-density power module has integrated gate drive and DC-link capacitors. The dynamic experimental results show that the proposed module has only 27% voltage overshoot, 2.1 times faster switching speed and the switching loss can reduce by about 57% compared with the commercial module. Furthermore, a half bridge inverter based on the proposed module is tested, which has 97.7% efficiency with a 0.9% improvement compared to the inverter based on the commercial module.
zhizhao Huang,
Huazhong University of Science and Technology
Wuhan, HUBEI

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