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Optimization of stacked substrate structure SiC half-bridge power module for low EMI
Keywords: SiC power module, parasitic parameters, electromagnetic interference
The high switching speed of SiC devices can increase the power density of the converters, but it also leads to higher electromagnetic interference (EMI) problem [1]. In order to reduce the EMI noise, one direct and efficient method is to reduce the parasitic parameters by power module design. [2] verified that the H-bridge diode rectifier module with vertical packaging structure has a low common-mode (CM) EMI. [3] verified a multilayer hybrid package structure with low parasitic capacitance which shows smaller CM EMI. However, these structures are constant geometry parameters. Actually, the parasitic inductance and parasitic capacitance should be a trade-off design for high efficiency and low EMI. Hence, This paper presents a 1200V/24A SiC half-bridge power module with ultra-low parasitic capacitance and inductance for low CM EMI. This module is improved from a stacked substrate hybrid packaging structure [4] by optimizing the copper pattern. The parasitic capacitance reduction methods and the trade-off optimization for geometrical parameters are given. Moreover, this optimization method can be applied to other 3D packaging structure. In the power module, the switching waveforms can be regarded as the EMI noise source and the parasitic capacitances consist of the noise path, thus the parasitic capacitances can affect CM EMI greatly. Among these parasitic capacitances, the high dv/dt caused by switching mainly lies in the output node of power module, which makes the capacitance between output node and heatsink the main path of CM current. That means we can suppress CM EMI by decreasing this capacitance. At present, most commercial modules use a single-layer structure, but it has less freedom in capacitor optimization. The proposed power module in this paper adopts a three-layer structure and thus has higher design freedom. The capacitances of neighboring layers are proportional to the area of copper and inversely proportional to the thickness, while the capacitance between the top and bottom layer is almost 0 because of the shielding effect. Therefore, the proposed module is designed by following criterion: 1) the output copper area on the DBC should be as small as possible; 2) the output copper for connecting with the external circuit should be placed on the top layer; 3) some other copper pattern can be placed under the output copper pattern for shielding. The whole module consists of a layer of PCB and a layer of DBC, SiC dies are connected by solder and bonding wires. The following principles are considered in the module design: 1) The upper layer of the power module uses a PCB to facilitate the integration of the external circuit and the driver circuit. And it also reduces the parasitic inductance brought by the extra terminals. 2) The lower layer of the module is DBC, which is connected to the PCB through solder. The hollowed window of PCB allowed the SiC die soldered to the DBC for better heat dissipation. Different layers and the chips are connected by through via-holes and bonding wires. 3) Minimize the area of the copper layer of DBC connected to the SiC die, M2 and D2, and move the routing connected to the external circuit to the top layer of the PCB in order to reduce certain parasitic capacitance. 4) The current flows from the top layer of the PCB and flows out from the button layer of the PCB on the same side. The loop is designed as close as possible to reduce the parasitic inductance by mutual inductance cancellation According to the simulation results ,by ANSYS Q3D, the output node capacitance decreases from 21pF to about 7pF, while the parasitic inductance of power loop increases from 3.8nH to 5.5nH in consequence. In order to verify the impact of the parasitic parameter changes in the proposed module on the switching process and conducted EMI, the performances of two power modules are compared by simulation and experiment. The simulation is carry out with gate resistor 20Ω, switching frequency 300kHz under 400V/20A by software LTspice. The SiC MOSFETs and diodes are C2M0080120D and C4D10120D. The simulation results show that the switching speed of the proposed power module decreases slightly, and the switching loss increases from 122.4μJ to 126.2μJ, but actually the differences are not significant. However, the CM EMI shows about 9dB decrease, which is quite significant. The experimental result of the double pulse test shows that the switching speed of the proposed power module also decreases slightly, and the switching loss of the proposed module and the original module are 189.8μJ and 192.8μJ respectively. And the maximum decreasing amplitude of CM EMI is about 6dB.
Yue Xie,
Huazhong University of Science & Technology
Wuhan, Hubei
中国


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