Here is the abstract you requested from the imaps_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Study PID(photo imageable dielectric) and non-PID on process, fabrication and reliability by using panel glass substrate for next generation interconnection.|
|Keywords: panel level , RDL, PID|
|In 1965,Gordon E.Moore, the co-founder of Intel states that the number of transistors on a chip will double every 18 months and his theory called the Moore's Law. The law has been the guiding principle of chip design around 50 years. The technology dimension is scaling very aggressively in IC foundry. For example, TSMC announced their 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high performance computing applications. It is scheduled to start risk production in the second half of 2019. To overview the semiconductor supply chain included IC foundry, wafer bumping, IC carrier, PCB(Printed circuit board) and OSAT(oversea assembly and testing)…etc, the IC carrier and PCB(Printed circuit board) technology dimension scaling are far behind than the IC foundry since many reasons for the traditional industry. The industry need different kinds of breakthrough approaches for the scaling of via and strip line in next generation interconnection. Traditional organic substrates faces many challenges of warpage, surface roughness and material dimension stability issues for manufacturing and high density I/Os with very fine line interconnections. To breakthrough these challenges, the materials of glass carrier, new PID(photo imageable dielectric) and advanced equipment were evaluated for the fine line and fine via interconnection. In the papers, there are many PID(photo imageable dielectric) and non-PID materials were surveyed and compared for fine via(< 10um) interconnection or low loss of high frequency application. The candidate one was choose for redistribution layers (RDL) fabrication by using 370mm x 470mm glass panels. Semi additive process (SAP) was used for direct metal metallization on glass panel with different build-up dielectric materials to form daisy chain test vehicles. The process, fabrication integration and electrical measurement results of daisy chain showed good continuity and electric resistance in the glass panel substrate. The reliability of the temperature cycling test (TCT) and highly accelerated stress test (HAST) test were evaluated as well in this study.|
|Chun-Hsien Chien, Deputy Director