Here is the abstract you requested from the imaps_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Investigation of new combination usage of dicing tape and backside coating tape for|
|Keywords: Stealth dicing, Wafer Level, Backside protection|
|Information terminals including smart phone and tablet devices have been advanced toward high functionality. Therefore, downsizing and thinning of built-in semiconductor package have also been accelerated. The market situation requires thinning of silicon wafers, downsizing of chips and, Micro Electro Mechanical System (MEMS) appeared in the market. Some kinds of MEMS have very brittle structurers like a membrane. When such kind of thin wafer is singulated using current blade dicing process, mechanical pressure of dicing blade should cause chipping of Silicon wafer. Similarly, when such kind of brittle MEMS wafer is singulated using current blade dicing process, cooling water can cause breaking of membrane structure. Furthermore, UPH of current blade dicing process for small chip is normally not so high. “Stealth dicing” process is viable solution for such problems. “Stealth dicing” forms modified layer in silicon wafer by focusing laser inside the silicon wafer then. The silicon wafer is singulated by cool expander. “Stealth dicing” doesn't use any mechanical cutting tool, so it prevents chipping. “Stealth dicing” process is totally dry process doesn’t use water. So, it can prevent breaking of membrane structure. Furthermore, the cutting speed can be higher than blade dicing. It means “Stealth dicing” UPH is higher. Additionally, “Stealth dicing” cutting width can be narrower than blade dicing. It means “Stealth dicing” can improve the yield constant of chips per wafer. If the laser is irradiated from circuit side, pollution of circuit might be caused, or the metal pattern in circuit might prevent the laser from focusing. Therefore, laser irradiating from backside via the dicing tape became mainstream. Meanwhile, “Stealth dicing” process can also be applied to other materials like GaAs, GaN, Glass, Sapphire and SiC beside Silicon. The suitable wavelength of laser differ by material types. Hence, the dicing tape for “Stealth dicing” process requires high transparency in wide range of wavelengths. Backside coating tape (Adwill LC tape® series manufactured by LINTEC) for Wafer Level Chip Size Package (WLCSP) has also been applied to “Stealth dicing process”. However, current backside coating tape’s transparencies are too low, so they cannot apply laser irradiation from back side in “Stealth dicing” process. Meanwhile, some identification markings should be scribed on the surface of backside coating tape by laser marker. High transparent material is normally not suitable for laser markings. The demand of “Stealth dicing” for the backside coating tape conflicts with the demand of laser markings on backside coating tapes’ surface. For the conflict demands, we finally found suitable materials and structure of backside coating tape through this study. In this study, we try to apply a new process for “Stealth dicing”. The process uses the backside coating tape paired with the dicing tape. The laser of “Stealth dicing” is irradiated from wafer backside through the backside coating tape and the dicing tape. As a result, we optimized laser, cool expantion and heat shrink conditions. To demonstrate the new “Stealth dicing” process, we successfully separated a 12 inch silicon mirror wafer with the backside coating tape of thickness 300 μm into 3 mm die squares.|