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|Dielectric Constant and Loss Tangent Characterization of Underfill Material Used in Flip-Chip Process|
|Keywords: underfill, characterization, flip-chip|
|To develop reliable high-speed packages, characterization of the underfill material used in the flip- chip process has become of greater importance. The underfill, typically an epoxy resin based material, offers thermal and structural benefits for the integrated circuit (IC) on package. With so many inputs and outputs (IOs) in close proximity to one another, the integrated circuits on package can have unexpected signal and power integrity issues if the electrical characteristics of the underfill material are not known and not accounted for. Furthermore, chip packages can support signals only up to the frequency where noise coupling (e.g., crosstalk, switching noise, etc.) leads to the malfunctioning of the system. Vertical interconnects, such as vias and solder bumps, are major sources of noise coupling. Inserting ground references between every signal net is not practical. For the solder bumps, the noise coupling depends on the permittivity of the underfill material. Therefore, characterizing the permittivity of the underfill material helps in predicting signal and power integrity issues. Such liquid or semi-viscous materials are commonly characterized from a simple fringe capacitance model of an open-ended coaxial probe immersed in the material. This method, however, is not as accurate as resonator-based methods. There is a need for a methodology to accurately extract the permittivity of liquid or semi- viscous materials at high frequencies. The proposed method uses solid walled cavity resonators, where the resonator is filled with the underfill material and cured. This characterization technique is simple, cost-effective, and has a high amount of accuracy. A minimal amount of machining ability is necessary. The cavities are assembled with a solid copper base and strips of copper aligned, drilled, and fastened around the perimeter of the cavity. Two pins are placed upright into the base of the cavity, protruding above the top of the cavity. These pins are placed a quarter of the length in from the corners of the cavity, diagonally with respect to the square cavity. Next, the cavity is filled with the underfill material and cured. Then, the filled copper cavity’s top surface is sanded till flush and square. Afterwards, the cavity is plated with an electroless copper plating solution, making the filled cavity completely enclosed. Finally, the port pins are milled so that there is a large enough clearance for the micro-probes. The cavities will be measured on a performance network analyzer (PNA) with ground-signal-ground (GSG) micro-probes. The first resonance frequency will be measured with enough data points to obtain well defined resonant peaks. The measurement is performed on several different sized cavities to characterize the underfill at various frequencies. Simulations of the same structure are performed in ANSYS HFSS and CST Studio Suite to compare with measurements. Since the dielectric constant and loss tangent have a frequency dependence, the electrical characteristics are extracted at multiple frequencies using the various cavity sizes. The accuracy of the simulations is just as important as the accuracy of the measurements in order to characterize the underfill material. The dielectric constant and loss tangent extraction process is a complex process, where all the physical characteristics of the cavities must be known or accurately measured. This includes the conductivity of the conductors, roughness of the conductors, the dimensions of the cavity, and the port pin locations. This paper discusses some of the challenges that are encountered when characterizing dielectrics with this method. This characterization methodology can also be used to characterize other materials of interest.|
|Robert B. Paul,
San Diego State University
San Diego, CA