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Development of EDA Techniques for Power Module EMI Modeling and Layout Optimization
Keywords: Electronic Design Automation, Power Electronics, Electronics Packaging
As wide bandgap (WBG) devices such as silicon carbide (SiC) and gallium nitride (GaN) transistors continue to develop and open more application areas, new packaging solutions are necessary in order to take full advantage of the benefits these devices offer (Rabkowski, Peftitsis and Nee, 2012; Millan et al., 2014). In the area of power electronics, WBG devices promise greater switching frequencies at higher voltages and temperatures than their silicon counterparts. These advantages can lead to a reduction in the size of passive components or cooling system requirements (Johnson et al., 2004). However, faster switching speeds lead to larger di/dt or dv/dt in the power loop—interacting with package parasitics and leading to overshoots and oscillations that contribute to electromagnetic interference (EMI) (Busatto et al., 2005; Oswald et al., 2014). Similarly, as power module packages tend towards higher density designs, proper placement of devices becomes critical to avoid mutual heating effects and mitigate thermal management issues (Seal and Mantooth, 2017). These concerns require careful evaluation of the trade-offs associated with power module layout and die placement in the early stages of package design. Since designing electronic packages is a multi-domain problem, common approaches make extensive use of finite element analysis (FEA) and transient circuit simulation to predict the electro- thermal response for a given physical design(Hammadi, Choley and Penas, 2011). However, this can be computationally expensive and places a large burden on the designer in preparation for FEA simulations. To overcome these issues, this team continues to develop an electronic design automation (EDA) tool— PowerSynth—for power module layout using reduced-order models in a multi- objective optimization framework.

In its current iteration, PowerSynth takes input from the package designer in the form of a simplified layout and design rules as specified by a manufacturer design kit (MDK)(Main, 2017). PowerSynth then uses a genetic algorithm to alter trace geometry and die placement with goals including minimization of electrical parasitics and device junction temperatures. Estimation of package parasitics is performed using response surface modeling (RSM) techniques where pre- computed parasitics data are fit to a function based on trace geometry and spatial position(Le et al., 2017). Similarly, die temperature rise is predicted using a fast thermal model characterized using a single FEA simulation which is then reduced to a 1-D thermal impedance network with additional thermal resistances accounting for relative locations among devices and trace edges(Shook et al., 2012). The performance of both the electrical parasitics model and thermal model has been verified through simulations and physical measurements to show good agreement among the results while reducing computation time by up to three orders of magnitude(Evans et al., 2018). Using these models within its optimization framework allows PowerSynth to then present users with hundreds of candidate-designs along a Pareto frontier within minutes. Selected solutions can then be exported to several commercial FEA tools or as a parasitics netlist for further analysis and verification before prototyping. Additionally, by using an MDK, only feasible designs are among those reported to the user— further reducing time and overhead associated with the early stages of physical design.

As the development of this tool has progressed, the need to incorporate EMI-aware layout design has become of greater interest. To this end, research has begun on incorporating models and methods to produce layouts with reduced EMI noise generation while simultaneously accounting for impact on device temperature and overall parasitics. Conducted EMI modeling in this work is currently based on high-frequency equivalent circuits as outlined in (Lai et al., 2006). These circuits are populated using results from parasitic extraction using PowerSynth and evaluated using modified nodal analysis (MNA) in the frequency domain (Vlach and Singhal, 1983). Excitations are provided to these high-frequency equivalent circuits using the Fourier transform of trapezoidal waveforms for noise-source voltage or current. The results of this MNA yield common mode (CM) and differential mode (DM) noise levels across the frequency spectra of interest. In order to assess the accuracy of the resulting noise spectra, a simulated EMI test bench has been developed. In this test bench, selected solutions are automatically exported from PowerSynth to a full-wave electromagnetic simulator where an s-parameter model of the package is extracted. This is combined with physics-based SiC MOSFET models (McNutt et al., 2003; Mudholkar et al., 2014) in transient circuit simulation to obtain the CM and DM noise spectra. Initial results using this method have shown good accuracy at predicting DM noise using PowerSynth.

Metrics and optimization strategies are currently under development to address EMI-aware layout design in PowerSynth. DM noise has been attributed to overall loop inductance and resonance with device output capacitance (Huang et al., 2003). CM noise in the conducted and radiated regimes has been attributed to the parasitic capacitance between layout traces and ground (Domurat-Linde and Hoene, 2012). By altering layout geometry and evaluating resultant EMI, the capabilities of PowerSynth will be further enhanced at the conclusion of this study. In this paper, a formal development of the proposed EMI evaluation methods and optimization metrics will be presented. These techniques will be implemented in PowerSynth and applied to case studies. Selected results will be compared with those from the simulated EMI testbench as well as physical measurements. The results of this work can benefit the power packaging community by providing further insight into, and reducing the time of, early- stage module development and system evaluation.
Tristan Evans, Graduate Research Assistant
University of Arkansas
Fayetteville, Arkansas
United States


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