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|Assembly challenges with Flip Chip multi-die and interposer-based SiP Modules|
|Keywords: System in Package (SiP), Flip Chip, Assembly Challenges|
|System in Package (SiP) modules provide integrated functionalities (processor, memory, power, etc.) in a small form factor as compared to PCB based individually laid out packages and passives. SiP modules face assembly related challenges as the complexity (multi die, large number of passives, through mold via (TMV) interposer for external memory, convergence of different technologies) of the package increases. This paper describes assembly challenges associated with a multi-die flip chip (processor, memory and power) module with plastic interposer for external Package-on-Package (PoP) memory. Three flip chip dice were processed using different bump structures with bump height variation and differences in coplanarity. Power management die designed for wirebond packages and flip chip interconnects were challenging due to probe damages on the pad. Hundreds of passives (0603, 0402, 0201 resistors and capacitors) were placed around the die with tight design rules. Different height components and tight spacing resulted in challenging topography for underfill dispensing leading to resin on top of passives resulting in electrical short. Reliability stresses exposed interfacial delamination on top of passives components. A two-layer BT resin- based interposer was used to provide electrical connection between BGA substrate and PoP package in a tight 0.4 pitch size. The interposer solder bump had significant voids (>25%) but no significant reliability risk was observed due to underfill strengthening of the bumps. In addition, use of molded underfill (MUF) material has the potential to eliminate delamination by reducing the resin rich material on top of passives. Laser ablation was performed to create TMV opening on top of interposers to connect PoP memory. Well-defined TMV opening profile, adjacent solder bridging, formation of cold joint due to poor coplanarity, and foreign material contamination were some of the challenges with stacking PoP memory (wirebonded BGA) package to the bottom of a SiP package. Overall assembly yield was ~95% during development and ~98% in production. Yield was improved by tightening design and process parameters for flip chip attach (bump shorting and cold joint), underfill (interposer tilt, voids, material creep, dispense pattern, volume), interposer (tilt, warpage, solder voids), TMV laser ablation process (exposed Cu, depth, width), and mounting of passives components (topography, misalignment, cap solder volume).|
|Akhilesh Singh, Package Engineer