Here is the abstract you requested from the imaps_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Ultra-thin Wafer Level Chip Scale Packaging|
|Keywords: ultra-thin, wafer-level-chip-scale-package, flexible|
|IC packages are getting thinner to facilitate thinner devices. Labels and tags are getting smarter, boards with embedded ICs are being developed and low profile requirements are needed to maximize product assemblies. Electronics are starting to bend, and reliability is in question. Semiconductor-on-Polymer (SoP) Chip Scale Packaging (CSP) is enabling ultra-thin flexible hybrid electronics and sensors today. These presentations shares the development of SoP CSP, and direct interconnect (DI) assembly of SoP CSP that has progressed from 24-pin attachment to System-on-Chip assembly of DI pitch at ≤100um in flexible hybrid electronics. Chip Scale Packaging (CSP) defines the logical end of IC package scaling in the package surface area (2D) as package area and IC size converge, for example in direct chip attach (DCA) applications. Scaling thickness is a key metric in packaging evolution. Die thickness is a key contributor to DCA and FC-BGA IC package thickness. SoP can be extended to IC packaging, by facilitating package thickness reduction and improved reliability for CSP/DCA and FC-BGA packages. The presentation also shows the technology roadmap for SoP application to IC packaging.|
|Doug Hackler, President