Here is the abstract you requested from the imaps_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Innovative Panel Plating for finer line spacing and better uniformity to allow semiconductor or embedded die assembly for Heterogeneous Integration|
|Keywords: Plating, Uniformity, EMIB|
|Panel Plating requirements are much more demanding as more applications migrate from Silicon to Panel assembly such as Panel level Fan Out to leverage the large sizes of the Panels. More recently Heterogeneous Integration like Intel’s Embedded Bridge (EMIB) or various other embedded die concepts are also pushing the boundary for typical panel structures. Line widths and spaces less than 10 Microns, thickness uniformity better than 10%, via topology free of voids and the same height as the redistribution lines are critical. Traditional Panel Plating Tools are mostly for bulk processing and are not designed to handle these additional requirements so a new tool was required to overcome these challenges. An Electroplating process is used with a Single panel per reservoir approach. An overhead transporter will bring the individual panels that will have been pre inserted in a rigid panel holder designed to handle large currents as well as reduce the warpage to a series of plating reservoirs as well as pre and post processing steps with the tool . The first process is to reduce voiding by removing all air in a vacuum chamber and then inserting degassed water in the same chamber to “prewet’ the panel. The Plating cells are customized for each metal layer but include a mechanism to allow the panel to be lowered in a structure with a shield to better align the electrical current between the material anodes and the Panel Holder as well as a louvered shear plate that is activated at a certain frequency to improve the seed layering. This whole mechanism needs to be very close to the panel and minimize any warping. This presentation will demonstrate that it is possible to achieve better line density, bump thickness uniformity and void free vias to allow semiconductor like assembly for Heterogeneous Integration on a standard Printed Circuit Board instead of more expensive semi additive processes or silicon interposers|
|Richard Boulanger, President