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In-Package Power Management with Single-Chip Power Converters
Keywords: Integrated Voltage Regulation, Power Management, Integrated Inductors
The generational scaling of CMOS device geometries, as predicted by Moore’s law, has significantly outpaced advances in CMOS package and power electronics technology. The number of transistors included on a typical digital CMOS die has increased by a factor of 100x with scaling from 130nm to 7nm CMOS geometries, while the number of I/O available on the die of the same size has increased only by a factor of 4x. Recently developed package technologies using silicon interposers offer higher I/O density, but with increased power delivery network (PDN) impedance that exacerbates power integrity challenges. Similarly, recently developed Wafer-Level Fan- Out (WL-FO) packages provide high packaging density, but at cost of thermal performance, which exacerbates power management requirements. The disparity in scaling of logic, package and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. The conduction of power to a high-performance integrated circuit (IC) die typically requires 60- 70% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur with generational advances in CMOS technology. Lower processor supply voltages increase processor sensitivity to supply voltage error, requiring reduced power delivery network (PDN) impedance or increased supply voltage margins, which degrade energy efficiency. Similarly, increased processor power density results in more aggressive load-current transients, di/dt events, inducing supply voltage undershoot that results in data-faults and compromises computational performance, or supply voltage overshoot that overstress the processor, reducing system reliability. These challenges with power delivery and efficiency substantially degrade the value proposition for transitioning high performance processors to next generation CMOS. Future compute architectures that alleviate the memory bottleneck by integrating memory closer to computing elements will likely accomplish this with monolithic 3D or 3D stacks of logic and memory devices. The I/O bottleneck and competition for data vs. power allocation will remain in these future compute systems, while the increased power density and impedance of power distribution through silicon interposers and 3D ICs further exacerbates power delivery and integrity challenges. Furthermore, the dearth of technology investment into power electronics for high- performance and mobile computing platforms has resulted in a glaring discrepancy in the performance and density of point-of-load power converters and the advanced integrated circuits that they power. Incumbent power management solutions rely on switched-inductor power converters with switching frequencies below 1MHz, which impose requirements for large discrete power inductors that occupy board area and significantly contribute to mass of the total solution. In this talk we will show that by integrating high-bandwidth power inductors with CMOS, we can efficiently operate power converters at >100x higher switching frequencies, enabling a >100x reduction in required inductor values and consequently, inductor volume and mass. The integration of power converters into processor packaging allows power to be delivered to the package at higher supply voltages and lower current levels, reducing volume, mass and cost of power management circuitry while alleviating the processor I/O bottlenecks. IVRs save power, space and cost for high performance electronic platforms by improving power management and power integrity, reducing current levels and associated power loss in the upstream PDN and reducing the volume and cost of bulky board- level power converter solutions. Package integrated Voltage Regulators (PVRs) provide a tremendous value proposition by further reducing package I/O allocated for power, while eliminating the need for upstream power- conversion stages and associated losses and cost. These benefits substantially reduce the size, weight and power of modern electronic systems. This talk will describe Ferric’s latest progress in the development of CMOS integrated, thin-film power inductors and the single-chip power converter chiplets they enable. We will illustrate several real-world applications of Ferric’s PVRs in various systems-in-package (SIP) along with an accounting of the size, power and cost benefits gained from integrating power conversion and management functions into the SIP. Typical systems realize a ~50% reduction in board-area, 15 - 40% reduction in power consumption and >20% reduction in BOM cost relative to incumbent power management solutions. The benefits realized to-date indicate that integrated power management will be a critical enabler of improved performance, power and cost in a post-Moore’s law industry.
Noah Sturcken, CEO
Ferric, Inc.
New York, New York
United States


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