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Flip-Chip Flux Evolution
Keywords: flip-chip flux, ultra-low residue flux, increased reliability
Flip chip accounts to more than 80% of the advance packaging technology platform, compared to Fan-In, Fan-Out, Embedded die and TSV (through silicon via). Flip-chip interconnect remains a critical assembly process: from large die used in artificial intelligence processors, thin die that warps at elevated temperature, heterogeneous integration in SIP application, flip chip on leadframe, to MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip- placement (DCP) technology. Then go on to examine the changing nature of the solder bump, the interconnect itself, and the substrate. From a standard solder bump, to micro Cu pillar bump, with different alloys; on different pad surface finishings of Cu OSP, NiAu to SOP (solder on pad); from regular pad on substrate to bond-on trace application; the many variables on flip chip assembly process will be discussed. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to TCB (thermocompression bonding) and the latest LAB (Laser assisted bonding) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Different types of flip chip fluxes, for example the commonly used water washable flux, the standard no-clean flux and the ultra-low residue flux; how these fluxes react to different processing methods, will be an area of discussion. Finally the paper will examine the need for increased reliability as the technology inevitably moves into the high volume, zero defect arena of automotive electronics.
Sze Pei Lim,
INDIUM CORPORATION
CLINTON, NY
United States


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