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|4-2-4 Laminate Hotspot Identification and Joule Heating Effect Assessment via Thermoelectrical Simulation|
|Keywords: self heating / joule heating, laminate design, thermoelectrical multiphysics simulation|
|Laminates or sequential build-up (SBU) laminate substrate comprised of dielectric materials, metal traces, and metal vias serve not only as the mechanical support for the Si ICs, but also electrically connect ICs to Ball Grid Array (BGA); by way of an embedded power delivery structure. The electrical current required to power the ICs is carried through spatially distributed metal traces and vias. The non-uniformity in the power distribution network may induce hotspots due to parasitic joule heating; especially in regions of high current density. Electrical packaging engineers need effective tools to identify, quantify, and mitigate hot spots in the laminate. Thermoelectrical multiphysical simulation provides a robust platform integrating the electrical, and thermal analyses for the study of joule heating in a complex design. Conventional simulations represent the detailed laminate wiring layout as a single planar with effective orthogonal material properties. Simplification provides a solution to the inherent simulation challenges encountered with a complex design (i.e. tiny characteristic lengths, high aspect ratios, excessive computational time and resources). Lumped model representation of the laminate greatly reduces the complexity of package level thermal model. However, simplification comes with a price. Information required to optimize the detail trace and via wiring physical design is unavailable in a solution incorporating an effective laminate structure; laminate joule heating as well as non-uniform trace wiring are left out. The laminate temperature profile is an average based on effective material properties. Without accurate joule heating evaluation, the hotspots cannot be identified or quantified. Overheating inside the laminate compromises signal speed and integrity, raises reliability concerns, and may even trigger catastrophic damage of dielectric material breakdown. This work introduces an iterative approach integrating the detailed laminate electrical design ECAD and package design to simulate the joule heating at package level with minimum simplification. The iterative SIwave- Icepak loop enables constant update of temperature (through ANSYS Icepak thermal simulation platform) and power distribution (through ANSYS SIwave electrical simulation platform) in each trace layer and via. The loop exit criteria is 0.5% and 1% difference between two separated iterations for temperature and power fluctuation, respectively. An accurate Joule heating assessment is achieved upon convergence. The solution captures the dependence on temperature of the material properties and of the Joule heating itself. The full package level structure including one 4-2-4 laminate, thermal interface material (TIM), solder bump layer with underfill, an IC with a power map, one copper lid, one heat sink and printed circuit board (PCB) to simulate in- situ package operating condition. As a baseline model (IC power 96 W, joule heating 8.4W), the temperature contour transition from laminate top to bottom layer shows that front metal trace layers are both affected by logic IC power propagation as well as local joule heating effect. The temperature variation of top layer and bottom layer are 10 °C and 15 °C, respectively. Influence from joule heating is investigated by comparing package temperature distribution with and without joule heating. Significant difference in overall maximum laminate temperature is observed with joule heating effect considered and also the temperature distribution is vastly different compared to no joule heating case. Joule heating in the laminate generates local hot spots in IC shadow region; especially in power layers. In real-life applications, absolute maximum temperature and its location inside the package are often the point of interest. Since the IC power and joule heating power are application and operational mode dependent, total laminate joule heating power as well as IC power will vary accordingly. Idle mode will consume less power compared to that of fully operation mode. To explore the dependency of maximum temperature and corresponding location, laminate joule heating power has been parameterized and evaluated in thermoelectrical model. A non- dimensional parameter power ratio (PR) in introduced to further expand applicability of joule heating impact findings. PR is defined as the power ratio between laminate joule heating and IC total power. Based on different PRs, absolute maximum temperature inside the package has been provided in this work. It can be seen at low power ratio (less than 3%), the maximum temperature is mostly dominated by IC power map. When joule heating increases, (i.e. higher PR at same logic die power), the temperature increment caused by joule heating effect further increases maximum temperature. In high PR cases, joule heating effect on laminate temperature contour reveals local thermal concentration. Not only maximum laminate temperature is increased, the corresponding location changes as well. Since critical temperature threshold inside the package also varies with applications: namely, 85 °C for memory module vs. 125 °C for ASIC module, it is more meaningful to keep track of relative temperature rise based on PR. Therefore, another dimensionless parameter, namely temperature rise ratio (ΔT%) is plotted against power ratio. Temperature rise ratio is defined as the ratio between temperature increments from no joule heating case to no joule heating maximum temperature. A total power dependent trend is observed from the PR%- ΔT% plot. After thorough investigation and analyses of laminate joule heating phenomena under different conditions, a predictive curve for maximum temperature rise percentage has been proposed to guide laminate wiring layout physical design and optimization. The predictive equation is validated by simulation data. As a result of this study, a systematic coupling methodology between detailed laminate electrical design and package thermal design is developed and analyzed. This approach exports accurate temperature distribution from laminate electrical design and captures the impact of laminate joule heating and highly irregular trace distribution of laminate into the thermal model. The power ratio (PR) clearly demonstrates that when joule heating exceeds 4-5% of logic IC power, hot spots require further attention in the thermal model. The PR identifies the threshold above which the detail thermal model is required for careful evaluation of the laminate temperature distribution.|
|ZHI Yang, Sr. Packaging/ Thermal Engineer
HOPEWELL JUNCTION, NY