Abstract Preview

Here is the abstract you requested from the imaps_2019 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Reliability analysis of bonding wire based on stacked substrate packaging structure
Keywords: Stacked DBC, Bonding wire, Reliability
Abstract The stacked substrate packaging technology is a new 3D power loop structure utilizing multiple layer DBC to achieve ultra-low parasitic for the fast switching SiC device. This structure has a different interconnection geometry between chips and substrate loop contrasting to the conventional module design, which needs optimization on the interconnection for the reliability of this new structure. Analytical models of different bonding wire shapes and DBC structures were developed to calculate the von-mise stress on each model under thermal cycling simulation. The simulation results show that the stress on bonding wire reaches minimum when welding point located at the center of the top DBC substrate and the stress decreases when DBC top copper layer thickness increases or ceramic layer thickness decreases. Moreover, bonding wires with smaller diameter, higher loop height and longer bonding distance show lower stress on the interconnection. Furthermore, thermal cycling tests were done on samples with same geometries of analytical models, and the wire pull test results showed consistency with the stress calculation results on verifing the optimum wire shape and DBC structure for the stacked substrate packaging. Key words Stacked DBC; Bonding wire; Reliability I. Introduction In order to fully develop the high-speed switching potential of wide bandgap devices, the stacked substrate packaging technology with ultra-low parasitic has been proposed in recent researches. The stacked DBC SiC module with 1.8 nH stray inductance is shown in Fig. 1 [1]. Since wire bonding interconnection plays a major role in power module failure mechanism, optimization on the interconnection is needed for this new structure. Bonding wire reliability of traditional wire-bonding modules has been studied in many aspects[2-5]. Zhao Jingyi finds that parabolic shape bonding wire has the minimum von-Mises stress indicating the best reliability [6]. Through analytical models on heel stress and fatigue tests of the different shaped wire bond, B. Czerny finds that high and angled wire shape has the best lifetime result [8]. To study and predict the fatigue life of wire interconnection, Qiuxiao Qian and Yong Liu establish models with different encapsulations and find the effect of encapsulation on the bonding wire fatigue mechanism through simulations [7].However, researches on wire bonding interconnection between chip and multi-layer DBC has never been discussed. The subject of this paper is to investigate a optimum shape of bonding wire and DBC structure for stacked substrate packaging. Models of different wire and DBC geometries have been analyzed and thermal cycling tests on samples with same model geometries have also been done. Von-mise stress on models under thermal cycling simulation has been calculated to find the interconnection geometry of minimum stress, indicating the best reliability. Wire pull test on the samples will be done to help validating the reliability of different interconnection geometries.
Chi Zhang,
School of Electrical and Electronic Engineering at Huazhong University of Science & Technology
Wuhan, Hubei

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Rochester Electronics
  • Specialty Coating Systems
  • Spectrum Semiconductor Materials
  • Technic