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Designing Software Configurable Chips and SIPs using Chiplets
Keywords: Reconfigurable, SIP, Chiplets
zGlue Smart Fabric, an active silicon interposer, enables rapid development of SiPs and Chips using chiplet stacking in a modular style. The main application for the rapid development is the high-mix market for ultra-low-power systems such as connected smart devices. The design of Smart Fabric interposer is such that its development NRE cost can be amortized over usage of a number of different products by simple downloading of a schematic into the interposer to program the interconnectivity of chiplets. The interposer also holds key common functions that make it active. Two such essential functions are built-in self-test, and voltage/power management. With the integration of such functionality in the interposer, the material cost of the interposer gets offset due to reduction in the bill of material. In addition, built-in self-testing and correction enables manufacturing yield recovery and enables use of loose tolerance manufacturing lines. A key aspect of the zGlue interposer is its ability to work with off-the-shelf chiplets in known good die (KGD) and wafer level chip scale package (WLCSP) format without dictating a footprint constraint on chiplets. This is achieved by making a fine pitch bump array on the zGlue interposer. A single ball on the chiplet die comes in contact with multiple bumps on the zGlue interposer, later referred to as a ‘one-to-many’ scheme. This way a spatial over-sampling of the die solder-balls ensures that zGlue interposer can attach to off-the-shelf IO solder ball geometries. A localized switch underneath each zGlue micro bump can then be programmed to connect it to power, ground, and different signal buses. Connection to the RF and sensitive analog signals are handled in RDL. Programmability of zGlue bumps also opens up the possibility of repair after manufacturing. A built-in self-test scheme for electronic re- alignment makes it possible to compensate for the X, Y and angular misalignment in the attachment of dies to a certain degree which alleviates one of key the manufacturing cost challenges. The design process with zGlue includes usage of a cloud-based software design tool called ChipBuilder (http://chipbuilder.zglue.com). This tool performs most of conventional SiP design functions but more importantly it is used for creating soft and hard routes among IOs. ChipBuilder starts with a data representation of zGlue Smart Fabric. A growing library of chiplet data has been encoded into the tool and is made available to the users of ChipBuilder via internet. Users can browse through available chiplets, view their salient features, add new chiplets, and can use these chiplets to create custom chips and SiPs. Design entry features for schematic, IO planning, and SPICE netlist generations allow the user to capture full design intent following by design optimization functionality. To validate and characterize the ‘one-to-many’ chiplet ball to zGlue copper pillar solder joints, an assembly development test vehicle was designed and manufactured. As part of this test vehicle development, we validated the manufacturing challenges and design rule optimization for such kind of assemblies. The DOE was carried out with wafers processed to have a top metal finish with four grid configurations of copper pillar micro-bumps with varying pitches and diameters. These wafers were used as die-to-wafer Interposer and further processed to assemble chiplets on top. Nine test spots were chosen on a wafer to assemble 5x4 chiplets in the 2 by 2 grid of different copper-pillar spacing and arrangement. Each interposer die on the test wafer is divided in four quadrants a) a 5 mm x 5 mm section of micro-bumps at 100 µm square pitch, b) a 5 mm x 5 mm section of micro-bumps at 100 µm hexagonal pitch. C) The other two quadrants had the same micro-bump geometry at 70 µm pitch. Pitch and packing variations were added to understand any solder wetting and bridging issues which may arise. This type of assembly had not been attempted using a high-volume production process with pick and place machines, and solder reflow ovens. The assembly experiment included manufacturing of the substrate wafer followed by assembly of five of-the-shelf chiplets. The assembled chiplets included wafer level chip scale package parts for Bluetooth Low Energy Radio, ARM Cortex M4 micro-controller, an accelerometer, a geomagnetic compass, and a MEMS real time clock chip X-ray characterization of the parts shows good connectivity and no signs of solder bridging defects. During the verification of the surface mount die stacking, no obvious defects such as tombstone, missing die, swerve, or insufficient solder were discovered. After placement, the wafer was subjected to solder reflow using production surface mount ovens. No obvious defects were found with chiplets after reflowing with the exception that unqualified chiplets acquired from the vendors had missing or misplaced solder balls. The primary zGlue Smart Fabric technology has been validated. An important feature of the technology is the footprint agnostic assembly of components in a cost conscious and high- volume compatible manner. The complete technology validation encompassed design, assembly, quality, engineering samples, and readiness for volume production. With the successful delivery of the zGlue technology, a path to development of a new area of 3D-IC has opened up. With this modular IC design style, we are able to support an ecosystem and effectively handle high-mix low volume devices that we expect with the growth of connected smart devices everywhere.
Jawad Nasrullah, CTO
zGlue Inc
Mountain View, CA
USA


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