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|Novel vertical stack embedding die technology in flexible printed circuit for electronics miniaturization|
|Keywords: Embedding Die Technology, Flexible Printed Circuit, High density packaging technology|
|Miniaturization of electronics module is always required in various fields including medical application like hearing aid and implantable devices. Many types of high density packaging technology has been proposed and used to realize miniaturization, for example package-on-package, bare-die stack, flex folded package and Through Si Via (TSV) technology etc. Embedding die technology is one of the promising technology to realize miniaturization and there are several types of embedding die technology on market which mainly use multilayer substrate and Cu electroplated connection. To realize further miniaturization by using the embedding die technology, simple way is to embed multiple dies in vertical stack, however, there are challenges on layer counts and yield management coming from build-up process of multi-layer substrates. Especially yield management is key factor for complex embedding die module. Once the first die is embedded in the substrate, if there is a defect at following build-up process, whole module will be discarded as they are no-repairable process after embedding dies. Therefore, embedding die technology is currently used only for relatively simple system in package structure like DC/DC converter and wireless module which has one embedding die with several passives on the embedding substrate. To overcome these situation, Chip-stack WABE Technology® has been developed, which multiple dies are embedded vertically in polyimide film. This embedding die technology is comprised of thin embedding dies (85um thickness), multi-layer polyimide/adhesive films and conductive paste. The embedding dies are sandwiched by polyimide films having Cu circuit (FPC) and the conductive paste makes electrical connection between layer and layer as well as layer and embedding die. By using the conductive paste, the process flow is “chip middle process” and can omit build-up process. Once each FPC layer is fabricated individually and conductive paste is filled with via holes, the embedding dies are mounted on certain layers. Then, all layers come together for one-step lamination process and they are pressed to cure adhesive material and conductive paste at a time. This one-step lamination process is regardless layer counts and it is more effective for complex embedding die module, in other words, increasing number of layer counts. In addition, automatic optical inspection (AOI) will be performed for all layers after fabrication of each individual FPC layer. The embedding dies will be placed only areas where pass AOI for all layers, whereas they will not be placed to the defected area detected by AOI. This inspection and one-step lamination process can avoid consuming expensive die without placing to the defected area. This paper describes detail of Chip-stack WABE Technology® and the fabrication result of test vehicle which has 6-die embedding dies (3-chips in vertical and side-by-side). The fabricated test vehicle has 14 copper layers with less than 0.9 mm thickness. They also showed semiconductor packaging reliability test with MSL (Moisture Sensitive Level 3) followed by thermal cycle test, temperature humidity test and high temperature storage test. These results show that the Chip-stack WABE Technology® is one of the most promising packaging technology for extremely miniaturizing electronic circuits for medical and wearable electronics.|
|Kazu Itoi, Technical Marketing Manager
Fujikura America, Inc.
Santa Clara, CA