Chip Scale Packaging for Power Devices
Fred Barlow, High Density Electronics Center, Electrical Engineering Department, University of Arkansas, 3217 Bell Engineering Center, Fayetteville, AR 72701, U.S.A., fbarlow@uark.edu, Phone: (501)-575-2374, Fax: (501)-575-7289
Abstract
While Chip Scale Packaging (CSP) has become a force in electronic packaging of low power electrical components, this technology has not yet become the dominant technology for power electronic devices. The reasons can be contributed primarily due to the greater constraints on thermal management as well as the intrinsic problem of a backside contact. However, the author believes that there are compelling reasons why power electronics can benefit from CSP. This paper discusses the issues with CSP-based power devices, reviews existing solutions, and introduces a new CSP power package developed by the author.
Key words: Chip Scale Packaging, Power Packaging, and Thermal Management.
1. Background
As most readers are aware, electronic packaging provides several functions: protection of the fragile electrical device, electrical connection to the outside world, and thermal management of generated heat1. In the past, these functions had normally been filled by lead frame packages such as SOIC, DIP, QFP, among others. CSP technology has been developed over the past 5-10 years in order to address the inherent inefficiency of conventional packages. In many cases, a conventional lead frame package consumes 4-5 times more space than the active device it supports. Since the active silicon device performs all of the electrical functions, the rest of the package is wasted space. CSP addresses this issue by creating a package that approaches 100% space efficiency while still protecting the active device. In addition, CSP avoids handling bare semiconductor devices that requires more specialized training and equipment due to the fragile nature of these crystalline devices. To date, bare die technology offers the greatest possible density, however, significant issues exist with Known Good Die (KGD).
CSP is normally defined as a package that is no more than 20% larger than the active device designed to contain it. The primary driver behind this technology has been the need for maximum utilization of space in a number of product areas. Products such as PCMCIA cards, and hand held consumer electronics currently require extremely high densities of electronic components. An additional benefit of these devices is improved electrical performance due to the reduced length of the associated electrical interconnects.
In contrast to low power devices, high power devices have a radically different set of packaging challenges. These devices are clearly very low I/O count, however, the reduction of parasitic effects in these connections is often critical due to the high current and voltage levels. In many cases, the component density is governed not by the size of the packaged device but by the ability to cool the devices, thereby, removing the often-large amounts of generated waste heat. In addition, these devices normally have an active backside terminal that is uncommon in low power electrical devices. This active backside contact greatly complicates packaging since a low resistance connection is required on both sides of the crystalline device.
2. Motivation
In spite of the challenges associated with development of CSP package designs for power devices, a number of compelling reasons exist for the use for these devices. Figure 1 illustrates the expected trend of system voltages and power levels for computers over the next five years based on industry predictions. For a variety of reasons, these voltages are rapidly dropping while power levels are steadily increasing. The result is a significant increase in current levels. These higher current levels create significant problems for power processing circuits since parasitic resistance and inductance can result in large power losses that reduce efficiency and create waste heat that must be removed to prevent overheating of the circuit elements. These trends have lead to the development of power devices that exhibit very low on-resistance values. However, in many cases, the wirebonds and the package lead frame are the limiting factor. In particular, new MOSFETs are now available that stretch the capabilities of the current generation of electronic packages.
The gate contact of a MOSFET is a low current contact that is used to control higher current levels between the drain and the source. However, for most power devices, a low inductance connection to the gate is important since it may limit the speed at which the device can be turned on and off. During each of the on/off cycles, significant charge must be added or drained away from the gate electrode. Any series inductance may limit the speed at which this process occurs.
The drain and source contacts are more critical in the operation since they must be able to handle high current levels with a minimum power loss. The on-resistance of a MOSFET is a measure of the intrinsic resistance of the device during the on-condition. This value represents the minimum amount of loss in the device given ideal packaging that contributes no parasitic resistance. Conventional MOSFETs have on-resistance values of ~10-100 milliohms. While this may seem like a very small value, consider a 100-watt DC/DC converter that converts 48V to 3.3 V. At an output voltage of 3.3V, the current at maximum rating would be 33 amps. At 33 amps, the power loss just due to a resistance of one milliohms would be ~1 watt. Even for the parallel combination of MOSFETS with ideal, zero loss, packaging such a converter, the power loss within the system can amount to watts of power. Conventional packaging will contribute a few additional watts of power loss to the overall system. While a few watts of power may not seem like a major issue, one needs to realize that each watt of power in this case represents a percent loss in efficiency, and generates additional problems for thermal management. As a result, a number of organizations have been developing low on-resistance MOSFETs to combat this problem3-7. MOSFETs with on-resistance values less than 10 milliohms and in some cases as low as a few milliohms are now commercially available. While these new devices significantly reduce this problem, they also create significant challenges for packaging engineers since the package may actually contribute more parasitic loss than the device it is intended to support. What is needed to full exploit the benefits of these new devices is a low loss packaging technology that introduces a minimum of parasitic resistance and inductance to the power device.
3. Potential Solutions
3.1. Wafer Level Packaging
The primary difference between low power devices and high power devices, as stated earlier, from the standpoint of packaging is the physical backside contact. Low power devices only require electrical connections to a single side since the backside is not active. In contrast, conventional power devices require connections to both sides. However, efforts are underway to utilize wafer level packaging to eliminate the need for a backside contact. The resulting devices can be packaged using conventional Flip Chip or CSP approaches.
International Rectifier currently offers power devices that are designed to eliminate the need for this backside contact. The resulting device has four or sixteen electrical contacts that are formed with the use of solder balls in the traditional Flip Chip configuration. The device surface is also passivated in order to prevent damage from the environment and during the handling process. To date, these devices are available with voltage ratings of 20 V and they are able to handle currents up to 5 A. These devices also offer very high packaging densities since the footprint of the device is equal to the size of the silicon die.
3.2. Chip Scale Packaging
A new approach to this problem is to package conventional power devices into a novel package that reduces the parasitic effects of the electrical connections. The author has developed a new power CSP package8. This approaches uses a metal lead frame that mates with the backside of the device while the topside contacts are created with solder spheres. The lead frame is designed to provide the shortest possible electrical path from the drain to the two package terminals on each end of the package. Solder is pre-coated on these terminals so that solder printing is not required to attach the device to an Insulated Metal Substrate (IMS) or Printed Circuit Board. The entire device surface is passivated in order to provide protection from the environment and during handling.
This package configuration has several advantages over conventional D2Pak or through-hole designs; namely:
• This design can be fabricated as a true CSP since the overall package size can be only slightly larger than the device.
• The source and gate connections are extremely short with minimal parasitic inductance and resistance.
• A short high conductivity metal contact is used to provide connection to the drain of the device.
• Effective cooling occurs on both sides of the device.
Figure 3 illustrates a top and bottom view of a power CSP prototype and provides a comparison with conventional surface mount and through-hole packages. All three packages are for the same MOSFET rated at 400V and 10 A.
This CSP is fabricated by first preparing a conventional power device for solder ball bumping. Since most power devices are provided with aluminum metallization, an under bump metallization (UBM) is required to effectively bond solder bumps to the gate and source contacts. This process may also redistribute the single source contact to a number of contacts in series, thereby greatly reducing the total source resistance. A nickel UBM was selected based on a zincation process described in detail elsewhere9. This process utilizes an electroless chemical plating process to first deposit a thin layer of zinc, shown in Figure 2, followed by the required thickness of nickel deposition. The result is ~ 2 microns of nickel which forms an ideal surface for solder ball adhesion, as illustrated in Figure 2.
The device is then bumped with solder spheres and singulated from the wafer into individual dice. Each die is bonded into a lead frame that has been pre-coated with solder on both contact surfaces. The die surface is passivated to prevent damage of the fragile gate oxide.
The resulting power CSP package occupies ~50% smaller foot print than the conventional D2Pak normally used for the same device, and several times less space than a leaded through-hole design. In addition, the added parasitic resistance and inductance is several times smaller for all three of the device terminals.
4. Summary/Conclusions
These CSP packages allow a full utilization of the latest generation of MOSFETs since they do not contribute significant electrical parastics to the packaged device. In addition, the reduced space requirements are ideal for applications that have space restrictions.
Applications for these devices include a wide variety of products such as portable communication devices, battery chargers, DC/DC converters, Voltage Regulation Modules (VRM), and power supplies. In particular, applications that operate at high current levels will greatly benefit from the reduced losses and improved performance associated with this type of package.
About the author
Fred Barlow earned a Bachelors of Science in Physics and Applied Physics from Emory University in 1990, a Masters of Science in Electrical Engineering from Virginia Tech in 1994, and a Ph.D. in Electrical Engineering from Virginia Tech in 1999. He is currently working as an Assistant Professor in the Electrical Engineering Department at University of Arkansas.
References
1) C. Coombs, Editor, “Printed Circuits Handbook,” Chapter 3, “Advanced Packaging,” W. Brown, et al., McGraw-Hill, NY, 2002.
2) “Advanced Electronic Packaging with Emphasis on Multichip Modules,” W. D. Brown, editor, IEEE Press, NY, 1999.
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5) “CONCAVE-DMOSFET: a New Super-Low on-Resistance Power MOSFET,” Tokura Norihito, Yamamoto Tsuyoshi, Kataoka Mitsuhiro, Takahashi Shigeki, Hara Kunihiko, Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes & Review Papers, Vol. 34, No. 2B, Feb, 1995 JJAP, Minato-ku, Japan, pp. 903-908, 1995.
6) “Fifth-Generation MOSFETs Set New Benchmarks for Low on-Resistance,” Dan Kinzer, Power Conversion & Intelligent Motion: The Fusion of Power & Motion Technology & Applications, Vol. 21, No. 8, pp. 59-66, August 1995.
7) “New MOSFETs Cut Losses in High Power PSUs,” Charles Batters, Electronic Engineering (London), Vol. 70, No. 859, Jul-Aug, 1998, Miller Freeman plc, London, Engl, pp. 41-42, 1998.
8) “Power CSP,” Patent Pending, 2001.
9) “UBM Formation on Single Die/Dice for Flip Chip Applications,” S. Jittinorasett, F. Barlow, J. McGrath, and A. Elshabini, Proceedings of the International Conference on Microelectronics Packaging, IMAPS 1999, pp. 39-44, 1999.
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