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Advancing Microelectronics • Volume 28, No. 4 • July/August 2001

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Power Chip Interconnection: From Wirebonding to Area Bonding

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Xingsheng Liu and Guo-Quan Lu, Power Electronics Packaging Laboratory, Center for Power Electronics Systems, Virginia Tech, Blacksburg, Virginia 24061-0111, Phone: 540-231-3233, Fax: 540-231-6390, e-mails: xsliu@vt.edu, gqlu@vt.edu

Abstract

Wirebonds in power devices and modules are prone to high resistance, noise, parasitic oscillations, uneven current distribution, fatigue and eventual failure, with more demand on higher power density and better efficiency. Power semiconductor suppliers have been concentrating on improving device structure, density, and process technology to lower the on-resistance of MOSFETs and voltage drop of IGBTs. Recent advances made in power semiconductor technology are pushing packaging technology to the limits for performance of these power systems since the resistance and parasitics contribution by the package and the wirebonds are roughly the same as that on the silicon wafer.

These limitations have motivated researchers to seek new ways of packaging power semiconductor devices. To improve performance and reliability of packaged power electronics, wirebonds need to be replaced. Researchers have reported area-bonding technologies for interconnecting power chips using solder bumps and/or metal posts1-4. In this paper, the authors comparatively study fabrication issues, the electrical performances, the thermal management, and the reliability of wirebonding and area bonding technologies for power chip interconnection.

Key words: Power Electronics Packaging, Wirebonding, Area Bonding, Solder Bump, Metal Post, and IGBT.

1. Introduction and Background

To improve performance, efficiency, and reliability of packaged power electronics, alternative interconnect techniques, such as bond-wireless, are in need of development. There are several power packaging technologies under development to eliminate wirebonds. The authors introduced Die Dimensional Ball Grid Array (D2BGA) Chip Scale power package, solder bump Flip Chip technology, and metal post area array technology for power electronics packaging5. Recently, Fairchild announced that it developed BGA MOSFETs[6]; Paulasto et al.7 reported Flip Chip die attachment for multichip mechatronics power package; and Gillot et al.8 also proposed Flip Chip solder bump technology for interconnecting IGBT chip.

2. High-Density IPEM Challenges

Figure 1 shows a typical commercial power module. One can see that the wirebond module is a planar structure. The 2-D structure makes it difficult to realize full integration of gate drive, controller, passive components, and other sensor and communication circuitry. The bottom substrate accommodates power chips (the backside of the chips is drain), wirebond pads used to connect source and gate (top surface of the chips) to the substrate, drain, source, and gate tracks, and terminal leads connected to outside power buses. All these end up occupying a large area of the module substrate (non-silicon area). Consequently, wirebond module cannot fulfill the high density and size reduction requirement. Also, the long substrate tracks, and bonding wires contribute to parasitic inductance and resistance and increase the wire delay. Furthermore, this planar structure limits heat transfer to one direction. There is an increasing demand for high frequency, high-density, high performance, and more integrated power modules. Three-dimen-sional multichip mod- ules (MCMs) can meet the requirement for the future power electronics systems. However, a major technical challenge to be overcome is the lack of three-dimensional packaging technologies that can offer high-level of integration of power devices, passive components, driver circuitry, controls, sensors, and communication connections. Figure 2 is an advanced three-dimensional packaging concept that has been envisioned for IPEM packaging. The wirebond interconnected power devices are excluded from three-dimensional MCMs due to their large size, poor thermal management, and incompatible processing techniques. To move toward this concept, bond-wireless techniques for interconnecting power devices have to be developed.

Figure 3 shows the area bonding that was processed on an IGBT rated at 1200 V and 70 A (Tc = 25°C) using solder bump and metal posts. The device has source pads and one gate pad on the topside and drain on the bottom. For this application, all of the contacts were made solderable by a device/module manufacturer. Figure 3 (a) shows seven individual metal posts (1 mm x1mm x 2mm) that were soldered onto the source and gate pads, while Figure 3 (b) shows a single seven-post assembly soldered onto the device. Figure 3 (c) shows the solder bump interconnection of the IGBT chip. The as-packaged devices, which are essentially Chip Scale Packages, can be readily tested on a high-power curve tracer for static performance, and in a circuit tester for dynamic switching characteristics.

These Chip Scale Packaged power devices enable the realization of three-dimensional packaging of integrated power electronics modules shown in Figure 2. Several specific 3-D power module structures, as illustrated in Figure 3, have been developed for different applications using the CSPs introduced. The power CSPs are sandwiched between two metallic layers. The substrates are etched to the desired pattern. The bottom layer is an AlN DBC. The top layer can be a doubled-sided copper-clad laminate or AlN DBC. The IGBTs and the diodes are encapsulated using thermally conductive adhesive to help dissipate and distribute heat. For the structure shown in Figure 4 (a), driver and control circuits are built on top. For the design in Figure 4 (b), double sided cooling is realized. Driver and control circuits are built on the side of the power stage.

The manufacture process for wirebonding is also a concern. It was indicated that the most important limitation of wirebond has to do with the economics of chip usage itself. Wirebonding cannot be performed easily in manufacturing over the active area of chip compared to area-array solder bump connections, so the size of the chip is larger by about one-third with the wirebonded chip. This difference will increase cost, as it directly relates to the number of chips per wafer. Recent cost study also shows that area array solder bump Flip Chip is cheaper than wirebonding. Furthermore, wirebonding process for power chip packaging can cause reliability problems. The wirebonding technique for most of active power chips is ultrasonic or thermosonic wedge bonding. Bonding pressure, power, and temperature are the sensitive factors determining bonding quality. With a poor bonding pressure, it is impossible to form a good contact between wire and bonding pad. This fact may lead to a low fracture strength at the bonding interface.

Solder bump and metal post array techniques use solder reflow process. This offers high process yield and high quality bonding. The solder bump and metal post techniques make it possible for the power processing elements of a power module to be in the form of low-profile surface mount packages.

3. Electrical Performance

Contact resistance between the interconnect bonding and power chip pads, conduction resistance/voltage drop of the power devices, and parasitic inductance are the most important electrical parameters in power electronics packaging. Contact resistance and conduction resistance/voltage drop: These experimental tests show that wirebonding has higher electrical resistance than solder bump and metal post area bonding. The typical resistance value of wirebond itself is 2-3mW, while that of the area bonds is about 0.2 mW. The contact resistance between bonding wire and power chip pad is significantly higher than the contact resistance between area bonds and chip pad. Figure 5 shows the average contact resistance of in-house made wirebonding, commercial wirebonding, and area bonding. The inconsistency of the contact resistance makes the wirebonding worse. In Figure 5, the standard deviation of the contact resistances of six bonding on one IGBT chip is calculated and indicated in the Figure. One can see that the contact resistance of wirebonding is widely scattered (from 9.8 to 20.3 mW for in-house made wirebonding, and from 5.1 to 13.4 mW for commercial wirebonding), while that of area bonding is quite consistent. One would attribute this to the fact that wirebonding is sensitive to several process parameters, while the area bonding is a single-step reflow process, which is easily controlled. This inconsistency contact resistance causes uneven current distribution among wirebonds. The contact resistance for both the wirebond and area bond to the substrate is quite low and consistent. Altogether, area bonding cuts down interconnect resistance by about 65% compared to commercial wirebonding. Both posted and solder bumped power device chip-scale packages have lower conduction resistance due to the elimination of the wirebonds and other external interconnections such as the leadframe.

The wirebond module has large parasitic inductance associated mainly with the packaging of terminal leads, which is related to the planar packaging techniques. This inductance slows down the turn-on of the IGBT, causing turn-off overvoltage spikes, and turn-on voltage drop, increasing switching losses, and a peak voltage exceeding the device rating. Since the bottom conductor pads have to accommodate both wirebonds and terminal leads that carry a high current density, they end up occupying a large area of the module substrate (non-silicon area) and contribute to parasitic inductance. As more IGBTs are paralleled, the inductance of the conductor pads becomes more dominant. Parasitic modeling results showed that the low-profile solder interconnects have a significantly lower parasitic inductance, consistent with the observation of lower turn-off voltage overshoot. Modeling work attributed the majority part of reduction in parasitic inductance to the flexibility in laying out shorter current tracks as well as the benefit of canceling effect of mutual inductance in the multilayer structures.

4. Thermal Management

Wirebond modules are limited to one directional heat dissipation. The area array CSPs have an additional thermal path, the top solder bumps or metal posts. This makes three-dimensional cooling possible. One can see from the 3-D power module structures in Figure 2 that three-dimensional heat dissipation is realized. The main thermal path is the back of the power device. Due to the very short length and large contact area of a solder joint, the solder joint interconnection itself is a good thermal path. Thermally conductive encapsulant is the third thermal path, which helps transport heat away from power chips. A Finite Element thermal analysis indicated that 20-43% of the heat can be removed through the area joints.

5. Reliability Considerations

One major failure mechanism encountered in the state-of-the-art wirebond power modules subjected to thermal and/or power cycling is wirebond lift-off. Bonding wires are subject to a thermal stress due to the large CTE mismatch between aluminum wires and silicon chips when there are temperature changes during thermal/power cycling. This leads to bond fatigue and eventually failure. As mentioned earlier, poor bonding, potential chip surface cracking, and mechanical stress at the heel of wires due to the wirebonding process are also the sources of failure. The current imbalance in bonding wires, due to the inconsistency of contact resistance, proximity effect could cause some thermal problem, or even burn out the wirebond connection. Most of the IGBT chips of the failed modules are burned out either catastrophically or locally.

Electromigration might happen at a current density of about 10 4 A/cm 2 and at high temperature. The inconsistent contact resistance, high parasitics associated with the bonding wires, and the proximity effect of the wires cause uneven current distribution among the IGBT wirebonds and cells (within one chip as well as among the paralleled chips). If the current distributes non-uniformly among the IGBT chips, or wire debonding occurs at first, then the current density in some wires will be much higher than the average value and cause severe electromigration. In addition, high temperature plays an important role in thick wire electromigration, which accelerates the migration process.

The high current in the wirebonds generates high electromagnetic field, and since the wirebonds are so close to each other, strong mechanical forces are generated between wirebonds. This also affects the overall reliability of the power modules. The CTE mismatching between silicon chip and the substrate is the most important issue in area array 3-D modules. The area bonding techniques offer opportunities to reduce thermal stress by optimizing solder joint geometry, using compliant substrate and underfilling. The electrical modeling work also pointed out much uniform current distribution in the low-profile area array interconnects. Thermal cycling test showed that the area bonding is quite reliable.

6. Conclusion

The area bonding techniques and three-dimensional packaging structures have improved electrical performance, improved thermal management of power modules, and reduced sizes (improved power density). Area bonding offers lower and consistent contact resistance and can carry large current. The inter-connect resistance is cut down by 65% and the on-state resistance of the IGBT is reduced by about 30%. The parasitic inductance (and thus turn-off voltage overshoot) of die bonding and circuit tracks inside the 3-D modules is about 40% of that of wirebond modules. Therefore, power loss (conduction loss and switching loss) is greatly reduced. 3-D heat flow boosts heat dissipation capability in the proposed module structures. The area array interconnect techniques provide a solution of full integration of power devices, passive components, gate driver, and control circuitry.

References

1. Xingsheng Liu, Shatil Haque, and Guo-Quan Lu, “Three-Dimensional Flip Chip on Flex Packaging for Power Electronics Applications,” to appear in IEEE Transactions on Advanced Packaging, Vol. 24, No. 1, February 2001.

2. X. Liu, X. Jing, and G-Q. Lu, “Chip Scale Packaging of Power Devices and its Application in Integrated Power Electronics Module,” Proceedings of the Electronic Components and Technology Conference, ECTC’2000, Las Vegas, Nevada, May 2000.

3. X. Liu, S. Haque, J. Wang, and G-Q. Lu, “Packaging of Integrated Power Electronics Modules Using Flip Chip Technology,” Proceedings of the 1 th Annual Power Electronics Conference and Exposition, pp. 290 - 296, February 6 — 10, 2000.

4. S. Haque, K. Xing, R-L. Lin, C. Suchicital, G-Q. Lu, D.J. Nelson, D. Borojevic, and F. C. Lee, “An Innovative Technique for Packaging Power Electronic Building Blocks Using Metal Posts Interconnected Parallel Plate Structures,” IEEE Transactions on Advanced Packaging, Vol. 22, No. 2, pp. 136 — 144, 1999.

5. Xingsheng Liu, Jesus N. Calata, Jinggang Wang, and Guo-Quan Lu, “The Packaging of IPEM Using Flip Chip Technology,” Proceedings 17th Annual VPEC Seminar, Blacksburg, Virginia, pp. 361-367, September 1999.

6. A. Bindra, “ BGA MOSFETs Keep Their Cool At High Power Levels,” Electronic Design, September 20, 1999.

7. M. Paulasto and T. Hauck, “Flip Chip Die Attach Development for Multichip Mechatronics Power Packages,” IEEE/CPMT International Electronics Manufacturing Technology Symposium, pp. 433-439, 1999.

8. C. Gillot, D. Henry, C. Schaeffer, and C. Massit, “A New Packaging Technique for Power Multichip Modules,” Industry Applications Conference, Vol. 3, pp. 1765 -1769, 1999.

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