Lead-free flip chip bumping with special focus on stud bumping - a flexible and economical flip chip technology
Søren Nørlyng, MICRONSULT , Denmark, Tel: +45 44651457, Fax: +45 44651458, noerlyng@micronsult.dk, www.micronsult.com
Abstract
Due to coming environmental legislations, lead-free flip chip technologies are gaining increasingly high focus.
Of the various lead-free possibilities, stud bumping will be described in some detail. The flip chip stud bumping will shortly be explained together with the various joining technologies using either conductive adhesives or non-conductive adhesive pastes or films. The use of non-conductive adhesives (underfills) will result in and rely on a mechanical contact with the bump and pad held in compression due to the contraction or shrinkage of the adhesive after cure. Also metallurgical contacts — obtained by using solders or thermo-sonic or thermo compression bonding will be described.
Some focus will be on the so-called SBBä — Stud Bump Bonding — technology which is based upon a conductive adhesive joint.
Applications range from (mobile phone) CSPs, MCMs, SAW filters, MMICs, digital cameras, memory devices and hearing aids. Stud bumping addresses not only the very fast prototyping needs but also high volume, cost sensitive applications.
Applications with stud bumping and in particular SBB on a variety of substrates — glass, thick film ceramic, LTCC, FR4, micro-via and flex — will be described, together with the obtained high reliability data.
Introduction
Lead is one of the oldest materials used. However the toxicity of lead which is accumulated in the body can lead to brain, liver and kidney damage. Although the electronics industry accounts for less than 1% of the annual lead consumption, the main drive for its elimination is the risk that lead can leach from land-fill dumps of electronic waste to the ground water.
In the electronics industry the order of the usage of lead is solder (for joining), 70%, PCB finish, 25%, and finally component terminations, 5%.
Obviously focus is at lead-free solder alloys. The favourite p.t. is SnAgCu alloys with 3.5-4.0% Ag and 0.75-0.5% Cu. But quite common for the new lead-free alloys is their melting points higher than eutectic SnPb. SnAgCu melts at 217-218oC, this means reflow peak temperatures at 240-250oC, and therefore more expensive boards and more energy consumption for the soldering process.
The wetting of lead-free alloys are often not so good as with eutectic SnPb, so the self-aligning ability is reduced, which in turn calls for (more expensive) precise assembly equipment and the use of fluxes.
Therefore alternatives to solders are being re-looked upon.
Flip chip bumping
Normally solder flip chips are bumped as follows. The Si wafer has applied a UBM (Under Bump Metallisation) on the Al or Cu pads. A popular process has been the use of electroless Ni(P) and immersion gold, yielding a bump with a height mainly determined by the Ni-thickness around 5µm, the Au thickness being around 0.1µm. Other bumping techniques use a range of metals sputtered to the wafer and defined using photolithographic methods and subsequent etching. After this follows normally either plating of the solder alloy or stencil printing of the solder followed by a reflow to shape the bumps.
Alternatively the bumping is made using standard wirebonders. This is called stud bumping and will be the topic for the rest of the paper.
Japan has been leading in this development and several stud bumping approaches have been utilised, from the use of solder wire [1], copper wire [2], and gold wire [3], [4].
Joining techniques for stud bumps
After the gold bump has been created and formed using the wirebonder, a suitable technique has to be applied to make the electrical and mechanical connection to the substrate pads.
Depending of your end application, your required reliability, process compatibility, IC type, substrate type, etc., several possibilities can be offered. In the following some of the options will briefly be mentioned together with some references.
ACA
An-isotropic adhesives, or z-axis adhesives, are based upon an epoxy resin in which conducting particles – solids or plated plastic spheres – are added. The metals used are most often Au or Ni. The ACAs can be supplied as films (ACF) or pastes (ACP). By compressing the flip chip bumps in the pre-applied ACA, the metal particles are brought into contact under the protruding parts (bumps) and the substrate pads. This creates a conductive path in the z-direction only: bump to particle(s) to pad.
The process requires pressure (typically 90g/bump) during the mounting of the flip chip and during the curing of the adhesive. Due to the relatively high pressure the method is mostly used on flat and stiff substrates like glass, e.g., display drivers on LCD.
Lit. [5] describes the processing conditions and an application. [6] compares Au stud bumps with two plated Au bumping methods for test dies on FR4.
ICA
Isotropic conductive adhesives conducts current in all directions. Normally ICAs with Ag filler particles are used. The conductive adhesive can be applied to the pads on the board by stencil printing, but the most commonly used technique is by dipping, which also make fine pitch (down to 50µm-60µm) applications possible [7].
Matsushita, Japan has developed the SBB™ technology [8], [9], [10], [11], [12], [13], [14], [15], [16]. The SBB process is described in more detail later in this paper.
The dipping of the stud bumped flip chips in conductive adhesive takes place in a cup — fixed or rotating — having a very well defined height. It is important to have a fixed, well defined thickness of the conductive layer, so either a squeegee or doctor blade is used to level the surface after each dipping in the jar.
NCA
Non-conductive adhesives have also been used in connection with stud bumps [17], [18], [19]. It was early on realised by cross-sectioning flip chip assemblies with ACA that quite often the conductive particles were squeezed out under the bump when the assembly was compressed. The electrical connection thought to be through a link of conducting particles quite often was established as a mechanical contact between bump and pad, because the particles had been forced out.
So immediately work was done based upon non-conducting epoxies (underfills) into which the flip chip could be mounted with less pressure than in the case with ACA. Pressures of 30g/bump or less for 5sec @ 220oC have been reported [20]. When the adhesive cures, it shrinks and brings the bump-pad-contact in a state of compression which ensures the long term reliability.
Solders
Where the applications have involved flip chip on board including maybe more flip chips and passives, the need for a repairable process and a process compatible with the joining of the SMDs can have importance.
IBM-Yasu has described the use of solder based upon SnPbIn jetted to the board for modem applications [21]. The Au and In creates an intermetallics layer on the boundary between the Au and the solder, which interrupts the Au diffusion into the solder. NEC has described, [22], a fluxless flip chip interconnection technology with Au stud bumps and Sn3.5%Ag solder.
The solder is applied on the board by jetting.
Ultrasonic
The “normal” flip chip applications involve some way of underfilling a non-conductive resin between the flip chip and the board surface after the flip chip balls have been joined with the pads on the substrate.
The underfill ensures that balls do not crack or electrically create opens in the IC-pad to bump to substrate-pad connections when materials with dissimilar TCEs are joined and temperature cycled [23]. The function of the underfill is to redistribute the thermo-mechanical stresses away from the solder joints.
But some ICs are not well suited for underfilling. Either the IC can change properties or be destroyed (e.g., SAW filters and GaAs with air-bridges) or the electrical properties are changed because air as dielectric is being replaced with epoxy as dielectric (e.g., in some RF applications).
In these cases a mechanical bonding of the bump material to the substrate-pad is needed.
Ultrasonic (US) bonding can be used [24], [25]. The bumps are normally flattened before the US bonding.
The connection is made by force (75g/bump to 40g/bump today), heat (200oC or RT today), US energy and time (down to 0.5 sec today).
In the case an environmental protection is required, “sidefilling” the dies with an underfill variant can be used. This is a product which does not tend to make capillary flow. It has modified thixotrophy or can be snap-cured using UV light.
Thermocompression
Alternatively thermocompression bonding can be used [26]. Here the connection is made with heat (300oC), pressure (150g/bump) and time (20 sec). Again the bumps are normally flattened before the bonding.
Stud Bump Bonding, SBB™
As earlier mentioned this paper will concentrate on the use of one specific flip chip technology, the Stud Bump Bonding, SBB technology. It was originally developed by Matsushita, Japan, and is now used in several variants all over the world.
SBB relies on a truly lead-free, fluxless joint based upon the use of a flexible conductive adhesive which takes up eventual movements during processing and the thermal excursions between the TCE mismatched chip/substrate combinations.
SBB lends itself to fast prototyping as well as high volume production.
Processing
The process starts with the studbumping of whole wafers or individual ICs. The gold wirebonding is normally done using automatic ball bonders. The speed is currently 14-16 balls per sec. [27]. The bonding wire is quite often Au1%Pd, which eases the breaking of the wire tail after the bump formation. After the studbumping, the wafer or the die is coined, which means that the tails of the bumps are compressed in a tool to approximately the same height (within ±5µm). Some wirebonders can offer this via a tool on the machine or eliminate the coining via a consistent bonding/wire-breaking process.
After this levelling, fig.1., the bumped flip chip is dipped in the cup with conductive adhesive. If the height of the adhesive is well controlled (normally 2/3 of the height of the bump incl. the coined tail), the adhesive will only be applied on the top and the upper sides of the stud bump, with no risk for shorting the neighbouring bump.
Fig.2 shows a bump after the dipping.Then the flip chip is placed or mounted to the substrate pads and the conductive adhesive is cured.
After the curing the flip chip is now electrically joined with the substrate and the assembly can be tested if needed.
If the chip shall be replaced this is easily done because the conductive adhesive being thermoplastic in nature offers only a limited adhesion strength. The process can now be repeated with a new die placed, cured and tested. When OK the flip chip is underfilled and cured.
Advantages
SBB™ offers the users several advantages.
Any die that can be wirebonded, can be stud bumped. You can work with standard commercial available bare dies (without UBM).
Already when the first ICs are received in waffle trays or as part of a Multi Project Wafer, the dies can be bumped and flip chip mounted. Single dies, section of wafers as well as full wafers can be (stud) bumped.
This means very fast Time To Market, TTM.
There is no need for an often time consuming or costly UBM process.
SBB™ handles due to the wirebonding operation very fine pitches – presently down to 50µm.
Fig.3 shows a stud bumped IC with 80µm pitch. SBB™ allows rework which can have importance in case of expensive dies.
Finally it should not be forgotten that SBB™ in comparison with soldering is a low temperature process. SBB™ can be applied on boards which do not stand normal soldering temperatures. This means that the boards for the adhesive SBB™ process can be cheaper than the laminates which will have to stand the very high soldering temperatures for lead-free solders.
The curing temperature for the conductive adhesive and the underfill is 150oC.
Limitations
As an adhesive flip chip process, the flip chip bonder needs more precision than required for solder flip chips, which can rely on self-alignment when the solder melts. If the application dictates flip chips to be mounted on the same side of the board as SMD components, the SBB process has to be applied first followed by solder dispensing, SMD assembly and reflow.
It is much easier if the SBB flip chips are mounted (first) on one side and the SMDs (then) on the other side. In this case the solder paste can be screenprinted as normal.
SBB™ Reliability
One of the advantages with SBB™ is actually the use of conductive adhesive in the joint. This means that the traditional solder fatigue problems are avoided.
The reliability of SBB™ on ceramic and organic boards are well described in the literature, [8], [9], and summarized in Fig.4.
Another advantage point using SBB compared with other adhesive techniques is the lower bonding force. It is well known that the very high mounting pressure for ACAs (around 80g/bump) not only can harm the IC but also cause deformation of organic boards. In comparison SBB has a bonding force in the order of 1g/bump.
SBB™ cost
Cost comparisons are always extremely difficult to interpret as apple-to-apple comparisons are hard to make.
The typical SBB cost comparisons, [28], take into consideration the number of wirebonders needed for a given number of IOs, the number of dispensers and flip chip bonders needed (investment/depreciation), the cost of consumables (length of Au wire, number of capillaries consumed, conductive adhesive, underfill), the number of operators needed and their monthly salary, the contribution from needed facilities (building, clean room) and utilities (water, air, etc.). This yields a figure of 0.2 yen/IO (@ 0.17 US cent/pin) @ 1M pcs./month for a 150 IO IC (excl. cost of IC and substrate).
Corresponding calculations for solder bumping incl. UBMs take into consideration (depreciation) the need for vacuum equipment to sputter the UBM, photolithography, screen printers, clean rooms etc. All in all showing comparable or higher figures.
Of course the wafer processing has an edge when the wafer size increases and the number of ICs per wafer and the total number of IOs increase. Basically the plating and solder printing is indifferent to the wafer size except for the depreciation of the necessary investments. When the investments have been made it is more or less the same cost to bump a 6” wafer as to bump a 12” wafer.
The stud bumping time increases linearly with the number of bumps per wafer.
On the other hand you only have to bump the good dies!
But basically the lowest total cost for the various technologies depends just as much on facts as it depends on “religion” — being biased for solder bumping or SBB.
SBB™ applications
When SBB™ was introduced in the end of 1980s the first applications were made on stiff, flat substrates like glass [3] and alumina [8]. Later followed applications on FR4 [9], then micro-via boards (ALIVH) [11]. Latest reported has been applications on flex [29].
The highest volumes are still seen on LTCC substrates for CSPs used in cellular phones with a monthly volume coming close to 5 M pcs. Other ceramic applications have been for MCM CPU-modules used in laptops and notebook computers.
Furthermore high volumes with the SBB technology are seen for CCD and CMOS cameras used on desktops, in laptops, mobile phones and Toyota’s (luxury) cars with navigation displays. Here the camera is looking backwards when reversing and the image is shown on the large display. The substrate is either FR4 or micro-via boards (ALIVH) depending of generation and size.
CSPs based upon ALIVH are being introduced (µCSP) in handheld applications due to their lower weight than ceramics. MCM-Ls (ALIVH) with several flip chips have been made for mobile phones.
Applications using flex are intended for light, dense modules, eventually stacked. Well suited for memory devices like the flash memory SD (Secure Digital) cards (developed by Matsushita, Toshiba Corp. and SanDisk, USA). The SD cards are used in (wrist watch) MP3 music players, DVD audio player, recordable DVD player, digital camera and mobile phones. Currently 64MB is available but pretty soon 256MB – and so on – can be achieved.
Also medical applications have utilised the high reliability of SBB, e.g., for the very demanding hearing aid applications where humidity and sweat makes up the tough environment for the devices.
Fig.5 shows a two chip application on thickfilm substrate 3mm x 5mm (Widex, Denmark).
SBB applications for microsystems have been described [30]. Here SBB has been used in the assembly of a delicate micro-machined silicon microphone including an ASIC.
SBB technology has also been utilised in RF applications for MMICs operating up to 30 GHz [31]. Here the substrate is a MCM-D based upon Si and BCB dielectric.
Conclusions
When miniaturisation demands the use of flip chips, no single technology will be the only solution. Fortunately many possibilities are at your hand depending of the applications, TTM, environment, reliability, cost and compatibility.
One very interesting technology, SBB, offers not only very fast prototyping and low cost for high volumes, but has also high reliability on a range of substrate materials and is a truly lead-free solution meeting the demands of tomorrow.
References
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