IMAPS Home Page
IMAPS Home Page IMAPS On-Line Industry Guide IMAPS Web Calendar IMAPS Membership Benefits IMAPS Advertising IMAPS Publications - Journal, Advancing Micro, CD-Roms... IMAPS On-line Membership Forms
























Advancing Microelectronics • Volume 28, No. 3 • May/June 2001
| Table of Contents | Previous Page | Next Page |
Lead – Free Solderability Preservative Coatings of PCBs

Zofia Morawska, Grazyna Koziol, Tele and Radio Research Institute, 03-450 Warsaw, Poland, Phone (48-22) 619 22 41 ext. 263, Fax (48-22) 619 25 10, E-mail: zofmor@itr.org.pl, gkoziol@itr.org.pl, WWW: http://www.itr.org.pl

Abstract

In order to maintain the solderability of PCBs over a period of storage time, it is necessary to protect the copper surface mount pads with solderable surface finish. Up to now the most common finish is eutectic tin-lead alloy by hot air solder levelling (HASL) method because it has the most desirable properties of ideal PCB surface. Unfortunately this coating does not meet the requirement of soldering pads planarity - fundamental factor for fine - pitch, very large scale integration (VLSI) surface mount technology (SMT) and contains lead - one of the most toxic metals. Alternatives to tin - lead (Sn-Pb) HASL finish may be co - planar, ecological coatings: electroless nickel/immersion gold (Ni/Au), electroless matt tin (Sn), organic solderability preservatives (OSP). All these lead - free finishes have been implemented in fabrication of PCBs at our Institute. This paper presents test results of PCBs with finishes: Ni/Au, Sn OrmeconâCSN and OSP Enthone™ Entek Plus carried out in comparison with Sn-Pb HASL coating. Solderability, surface insulation resistance (SIR) and shear strength of chip resistors 1206 solder joints have been tested in state “as received” and after accelerated ageing of PCBs.


1. Introduction

     Achievement of proper and reliable solder joints in electronic equipment depends on many constructional and technological factors including an adequate level of solderability of elements to be jointed, i.e., components and printed boards.

     The most common method of solderability protection of printed boards is coating the conductive copper pattern with Sn-Pb alloy layer almost eutectic in composition. The majority of PCBs produced are coated with HASL deposit. HASL’s dominance has continued over the past several years despite its serious technical limitations [1]. Boards manufactured in such a way, in spite of their solderability protected during storage are not suitable for all applications. Thus: fine pitch VLSI electronic components used in SMT require excellent planarity of solder pads on PCBs [2]. The requirement of planarity is not met by conventional HASL finish [3]. Examples of this problem solution may be the following lead-free finishes:

  • electroless, autocatalytic Ni/immersion Au,
  • electroless, matt Sn, Ormecon® CSN,
  • organic solderability preservative, En-thone™ Entek Plus.

     Finishing technology using above mentioned preservatives guarantees an excellent planarity of soldering pads without shock of PCBs. Ni/Au finish due to comparatively Au low thickness (0.1µm¸0.15µm) does not cause brittleness of solder joints made of tin based solder alloys [2, 4]. Its disadvantage is high production cost, what is a main reason of limitation in use of Ni/Au finish. Electroless Sn Ormecon® is an efficient, ecological and not expensive technology [5]. Recently OSP finishes are more and more used in PCBs fabrication [1, 6, 7, 8]. OSP process is the cheapest one among other preservative technologies and fully ecological.

     Apart from already quoted features these finishes must exhibit good solderability after manufacturing as well as after storage. Besides this the finishes should be compatible with alloys and fluxes used in electronics.

     To enrich the knowledge about lead–free PCB finishes and assess quality of PCBs manufactured in our Institute there were carried out solderability test, SIR measuring and shear strength test of soldered joints: chip resistors on PCB solder pads.

     The main purpose of our investigations was to answer the following questions:

  • Do electroless Ni/immersion Au, electroless Sn Ormecon®CSN, OSP Enthone™ Entek Plus PCB finishes guarantee solderability level required in electronics?
  • Is this solderability as good as solderability of conventional Sn – Pb coating?
  • Are the lead – free finishes presented in this paper a good alternative to the Sn – Pb HASL finish?

2. Solderability testing

     2.1. Test method and specimens

     Solderability tests have been carried out by the wetting balance method as in ANSI/J–J–STD–003 [9]. This method, as a dynamic one, allows to observe kinetics of wetting of the surface under test by molten solder in the presence of flux. The specimen coated with flux is suspended from a sensitive balance (typically a spring system) and immersed edgewise to a set depth and time in a bath of molten solder at a controlled temperature. The resultant of the vertical forces of buoyancy and surface tension acting upon the immersed specimen is detected by a transducer and converted into a signal which is continuously recorded as a function of time. The typical course of wetting process is illustrated by the curve in Fig.1.

     The solderability tests have been carried out on the test specimens as it is shown in Fig.2. The specimens were made of 1.5 µm epoxy-glass FR- 4 laminate, double sided with 18 µm copper foil and then they were adequately covered with preservative coatings as follows:

     Eutectic alloy solder bath 63Sn37Pb at temperature of 250°C and no–clean, low–solid, mildly activated fluxes have been applied for the testing. For Ni/Au finish TZ-3/ITR flux (based on organic esters of dicarboxylic acids and activated by dicarboxylic acid and organic salt) has been used and for Sn–Pb HASL, Sn Ormecon®, OSP Entek Plus coatings TN/4A/ITR flux (based on organic esters of dicarboxylic acids and activated by blend of dicarboxylic acids) was chosen.

     For solderability testing the Meniscograph Solderability Tester type MK6A hooked up to a computer has been used. Solderability tester set-up diagram is shown in Fig.3.

     The specimen has been immersed edgewise to 5 µm depth and held in this position for 10 s. The test boards have been tested in the following states:

  • “as received”
  • and after conditioning:
  • one time pass through IR reflow system,
  • dry heat, 4 h at 155°C ± 2°C, Test B [10],
  • damp heat, steady state, 10 days at 40°C ± 2 °C, RH, Test Ca [11], natural ageing, 3 months at laboratory conditions.


     For comparison purposes there have also been tested “bare” copper printed boards, directly after mechanical cleaning with pumice powder.

     2.2. Solderability criteria and requirements

     PCBs solderability criteria and require-ments are presented in the Table 1 as in ANSI/J–J–STD–003 [9]:

  • Wetting time tz [s] – time counted from the moment at which the specimen and solder bath first make contact until the moment when the contact angle is equal to 90° (only the buoyancy force acts on the specimen and the non – wetting state passes into the state of wetting).
  • Max. wetting force Pmax [mN/m] – it is the measured force Fmax [mN] per borderline unit (metallic part only) between specimen and solder.
  • Solder coating quality of the immersed surface estimated visually after withdrawal of the specimen from the solder bath.

     2.3. Solderability test results

     The test results: wetting time tz and wetting force Pmax are presented in Table 2.

     The examples of the wetting curves of specimens in the state “as received” are shown in the Fig. 4. Diagrams in the Fig.5 (max. wetting force Pmax ) and Fig.6 (wetting time tz ) illustrate PCBs solderability change after different conditionings.

     Solder coating quality of this specimen parts that were immersed in the soldering bath have been examined visually. It has been stated that all boards under tests, irrespective of the type of finish and the state of PCBs had been coated with bright, smooth, continuous and shining Sn63Pb37 solder layer without dewetting. The exception to this rule is OSP Enthone™ Entek Plus after conditioning at 155°C, 4 h; non – wetting and dewetting surface is more than 90%.

     Solderability test results show that:

  • all finishes under test exhibit good solderability level, because wetting force Pmax. > 120 mN/m, wetting time tz < 2 s and surfaces are covered with bright, smooth, continuous and shining solder layers without dewetting both in PCBs state “as received” and after natural and accelerated ageing,
  • an exception is OSP Entek Plus; this finish is not resistant against long – lasting, high temperature (155°C, 4h), because after this conditioning boards covered with this coating completely lose solderability (Pmax. = – 438 mN/m, tz ¥),
  • in state “as received” Sn-Pb HASL, Sn Ormecon and OSP Entek Plus present comparably high solderability level, higher than Ni/Au finish and “bare,” no – coated Cu,
  • natural and ac-celerated ageing reduce solderability of all tested finishes, but to a different degree,
  • for HASL, Sn Ormecon and OSP finishes there is evident a decreasing effect of conditioning types as following:
    • 10 days Ca > 4 h 155°C > 3 months natural ageing >1 pass IR system,
  • another relationship between solderability and conditioning types Ni/Au coating shows:
    • 3 months natural ageing > 10 days Ca > 1 pass IR system.

3. Surface Insulation Resistance Tests

     Surface Insulation Resistance (SIR) method [12, 13] is a quantitative method of assessment of electrical properties of insulation materials including surface resistance between conductive pads on PCBs. SIR of PCBs is affected also by the finishing technology.

     The test specimens (Fig.7) were made of 1.5 µm epoxy-glass FR- 4 laminate, single sided with 18 µm copper foil and then they were adequately covered with the tested finishes (see sub-close 2.1). For comparison purposes there has also been carried out a test with “bare” copper boards.

     For SIR tests the a-Metals Sirometer Model 300, software version 2.6 hooked up to a computer has been used. At first SIR has been measured under normal environmental conditions. Then the specimens were conditioned in a humidity chamber. At the first stage of conditioning in the humidity chamber the temperature was equal to 85°C and relative humidity (RH) 20%. After 3 h of stabilising the humidity slowly ramped up to 85% and the specimens have been allowed to reach equilibrium during one hour. Next the bias voltage +50V DC was applied for a period of 168 h. The measurements were carried out with 24 hour intervals. For the SIR measuring a voltage of –100V DC was used.

     The “comb pattern” test specimens meet requirements concerning surface insulation resistance ANSI/J–J–STD–004 [14] if after 96 h and 168 h conditioning in the humidity chamber SIR value is at least 100 MW. The SIR test results are presented in Table 3 and Fig.8.

     The results show that all the specimens under test meet SIR requirements that means: none of the investigated finish technology has a negative influence on surface insulation resistance of PCBs.

4. Shear Strength of Soldered Joints

     Soldered joints of electronic equipment during their exploitation are predominantly subjected to the action of shear forces. In our investigation the shear strength test was performed on the test PCBs (Fig.8) acc. to IEC 68-2-21 [15] and IEC 115-1 [16]. Solder pads were covered with tested finishes.

     Chip 1206 resistors have been soldered on PCB pads by an IR reflow process according to temperature profile as in Fig.9, using SnPbAg “fine – pitch” solder paste.

     Shear strength of soldered joints have been assessed after reflowing process and after conditioning at 145°C, 220 h. The shear force was applied to the resistor in the middle of its longer side, in parallel to the PCB surface, until destruction of the joint. The rate of force increasing was constant and equal to 20 N/s. The test results are presented in Table 4.

     As you can see in Table 4:

  • The highest shear strength has been obtained for joints soldered onto Au/Ni finish solder pads and this value was a little higher than for HASL and Sn Ormecon coatings.
  • After conditioning at 145°C, 220 h the shear strength of soldered joints has been reduced by about 6 – 8 % independently on finish type.

Conclusions

  • All of investigated PCBs finishes exhibit solderability level required in electronics both in the “as received” state and after natural and accelerated ageing.
  • OSP Enthone™ Entek Plus only is not resistant against long – term, high temperature action.
  • In the “as received” state finishes: Sn – Pb HASL, Sn Ormecon®CSN and OSP Enthone™ Entek Plus have comparable solderability and Ni/Au coating is characterised by a little lower solderability.
  • Natural and accelerated ageing decrease, but not reduce below required level, solderability of PCBs covered by investigated finishes.
  • All of investigated finish technologies have no negative influence on surface insulation resistance of PCBs.
  • Shear strength of soldered joints is more or less comparable for all coatings.
  • PCBs with all presented lead–free finishes are a good alternative to PCBs with Sn–Pb conventional finish for SMT applications.

Acknowledgements

     The authors would like to acknowledge the efforts of dr. K.Bukat, Mrs. S.Malczynska-Paz, Mrs.H.Hackiewicz and Mr. J.Sitek for their help with preparation of samples, carrying out the measurements and data plotting.

References

     [1] D.Cullen: “HASL Alternatives.” Printed Circuit Fabrication, July 1999, pp. 38–43.

     [2] H. Hackiewicz, Z. Morawska: “Some problems of Surface Mount Technology onto Electroless Gold Coated Printed Boards” (“Niektóre problemy technologii monta¿u powierzchniowego na pytkach zoconych chemicznie”) Elektronika (XXXVIII), November 1997, pp. 26–29.

     [3] J.Chwang: “PCB Surface Finish,” Surface Mount Technology, October 1995, pp. 20 and 22.

     [4] J.Chwang: “The Role of Gold in Solder Interconnection,” Surface Mount Technology, December 1994, pp. 18 and 20.

     [5] ȁNew Surface Finish for Printed Metal + White Tin,” Technical Bulletin of Ormecon Chemie GmbH & Co. KG., April 1998.

     [6] M.Carano: “OSP Evaluation,” Printed Circuit Fabrication, July 1997, pp. 28–31.

     [7] M.Carano: “Enhanced Solderability with Improved OSPs,” Surface Mount Technology, February 1998, pp. 134 and 136.

     [8] S.Platt, J.Brantingham: “OSPs and Real–World Manufacturing,” Printed Circuit Fabrication, February 1998, pp. 42–45.

     [9] ANSI/J–J–STD–003: “ Solderability Test for Printed Boards,” April 1992.

     [10] EN 600682–2:, “Basic environmental testing procedures. Part 2. Test B: Dry heat,” 1993.

     [11] HD 323.2.3. S: “Basic environmental testing procedures. Part 2. Test Ca: Damp heat, steady state,” 1987.

     [12] B.N.Ellis: “On insulation resistance,” Circuit World, vol. 21, No 2 1995, pp. 5–11.

     [13] B.N.Ellis: “The correlation between short– and long–term SIR testing,” Circuit World, vol. 22, No 2 1996, pp. 47–50.

     [14] ANSI/J–STD–004: “Requirements for Soldering Fluxes,” April, 1992.

     [15] IEC 68–20–21, Amendment 2: ”Basic environmental testing procedures. Part 2. Tests–test U: Robustness of termination and integral mounting devices.”

     [16] IEC 115–1: “Fixed resistors for use in electronic equipment. Part 1: Generic specification.”

| Table of Contents | Previous Page | Next Page |





 






 

[ Home ] [ IMAPS 2002 ] [ Chapters ] [ Calendar ] [ Publications ] [ Membership ]
[ On-Line Industry Guide ] [ Call For Papers ] [ Advanced Education Opportunities ]
[ MMRC ] [IMAPS On-Line Photo Album] [ Ceramic Interconnect Initiative ]
[ IMAPS Educational Foundation ] [ Discussion Boards ] [ Market Place ] [ Search]
[ IMAPS Web FAQ  ] [ Leadership ] [ Press Room ] [ Advertising ] [ Contact IMAPS ]


IMAPS-International Microelectronics And Packaging Society
611 2nd Street, N.E., Washington, D.C.  20002
Phone: 202-548-4001; Fax: 202-548-6115
IMAPS Website Privacy Statement
Terms And Conditions For Use Of Website

1997-2001 IMAPS